Variability in the execution of multimedia applications and implications for architecture
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Preemptive Multiprocessor Scheduling Anomalies
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Processor Pipelines and Their Properties for Static WCET Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Data cache locking for higher program predictability
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Analysis of the Execution Time Unpredictability caused by Dynamic Branch Prediction
RTAS '03 Proceedings of the The 9th IEEE Real-Time and Embedded Technology and Applications Symposium
Experimental Evaluation of Code Properties for WCET Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Design for Timing Predictability
Real-Time Systems
A Contribution to Branch Prediction Modeling in WCET Analysis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Journal of Parallel and Distributed Computing
Principles of Timing Anomalies in Superscalar Processors
QSIC '05 Proceedings of the Fifth International Conference on Quality Software
Modeling out-of-order processors for WCET analysis
Real-Time Systems
WCET analysis for a Java processor
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
Proceedings of the conference on Design, automation and test in Europe
Modeling the function cache for worst-case execution time analysis
Proceedings of the 44th annual Design Automation Conference
WCET estimation for executables in the presence of data caches
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Chronos: A timing analyzer for embedded software
Science of Computer Programming
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
A time-predictable VLIW processor and its compiler support
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the conference on Design, automation and test in Europe
Cache-aware timing analysis of streaming applications
Real-Time Systems
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
Predicated Worst-Case Execution-Time Analysis
Ada-Europe '09 Proceedings of the 14th Ada-Europe International Conference on Reliable Software Technologies
Using hardware methods to improve time-predictable performance in real-time Java systems
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems
Symbolic state traversal for WCET analysis
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Implementing time-predictable load and store operations
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multicore-aware hybrid code positioning to reduce worst-case execution time
Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
Resilience analysis: tightening the CRPD bound for set-associative caches
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
Abstract interpretation for worst and average case analysis
Program analysis and compilation, theory and practice
ACM SIGBED Review - Special Issue on the Work-in-Progress (WIP) Session at the 2009 IEEE Real-Time Systems Symposium (RTSS)
Cache and pipeline sensitive fixed priority scheduling for preemptive real-time systems
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
Ubiquitous verification of ubiquitous systems
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
WCET analysis of modern processors using multi-criteria optimisation
Empirical Software Engineering
Cache persistence analysis: a novel approachtheory and practice
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Branch target buffers: WCET analysis framework and timing predictability
Journal of Systems Architecture: the EUROMICRO Journal
Beyond loop bounds: comparing annotation languages for worst-case execution time analysis
Software and Systems Modeling (SoSyM)
Cache-related preemption delay via useful cache blocks: Survey and redefinition
Journal of Systems Architecture: the EUROMICRO Journal
Identifying irreducible loops in the Instrumentation Point Graph
Journal of Systems Architecture: the EUROMICRO Journal
WCET analysis of instruction cache hierarchies
Journal of Systems Architecture: the EUROMICRO Journal
Timing analysis and timing predictability
FMCO'04 Proceedings of the Third international conference on Formal Methods for Components and Objects
Worst-case execution time analysis-driven object cache design
Concurrency and Computation: Practice & Experience
Assessing the suitability of the NGMP multi-core processor in the space domain
Proceedings of the tenth ACM international conference on Embedded software
On the scalability of time-predictable chip-multiprocessing
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
Meeting real-time requirements with multi-core processors
SAFECOMP'12 Proceedings of the 2012 international conference on Computer Safety, Reliability, and Security
Cache persistence analysis: Theory and practice
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A hard real-time capable multi-core SMT processor
ACM Transactions on Embedded Computing Systems (TECS)
PROARTIS: Probabilistically Analyzable Real-Time Systems
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
Computation takes time, but how much?
Communications of the ACM
On-chip ring network designs for hard-real time systems
Proceedings of the 21st International conference on Real-Time Networks and Systems
Proceedings of the 21st International conference on Real-Time Networks and Systems
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Adaptive EDF: using predictive execution time
ACM SIGBED Review - Special Issue on the 5th Workshop on Adaptive and Reconfigurable Embedded Systems
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
Static analysis of multi-core TDMA resource arbitration delays
Real-Time Systems
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Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wrong in dynamically scheduled processors. A cache miss, for example, can in some cases result in a shorter execution time than a cache hit. Many examples of such timing anomalies are provided.We first provide necessary conditions when timing anomalies can show up and identify what architectural features that may cause such anomalies. We also show that analyzing the effect of these anomalies with known techniques results in prohibitive computational complexities. Instead, we propose some simple code modification techniques to make it impossible for any anomalies to occur. These modifications make it possible to estimate WCET by known techniques. Our evaluation shows that the pessimism imposed by these techniques is fairly limited; it is less than 27% for the programs in our benchmark suite.