Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
Program path analysis to bound cache-related preemption delay in preemptive real-time systems
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Cache behavior prediction by abstract interpretation
Science of Computer Programming
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Principles of Program Analysis
Principles of Program Analysis
An Accurate Worst Case Timing Analysis for RISC Processors
IEEE Transactions on Software Engineering
ILP-Based Interprocedural Path Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Efficient worst case timing analysis of data caching
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Accurate estimation of cache-related preemption delay
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Scalable precision cache analysis for preemptive scheduling
LCTES '05 Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
Scalable precision cache analysis for real-time software
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Resilience analysis: tightening the CRPD bound for set-associative caches
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Optimising task layout to increase schedulability via reduced cache related pre-emption delays
Proceedings of the 20th International Conference on Real-Time and Network Systems
Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system
ACM Transactions on Embedded Computing Systems (TECS)
Hi-index | 0.00 |
Tasks in an embedded system are scheduled either preemptively or non-preemptively. In case of preemptive scheduling, interferences on the cache of the preempted and preempting task may extend the execution times. The corresponding delay is referred to as cache-related preemption delay (CRPD). Lee et al. [6] presented a CRPD analysis using the concept of useful cache block (UCB): a cache block is useful if it may be in the cache before a program point and may be reused after this point. If a preemption occurs at that point, the number of additional cache misses is bounded by the number of UCBs. An upper bound on the CRPD of the whole task is thus given by the program point with the largest set of UCBs. In this article, we provide a survey of the state of the art techniques to bound the CRPD, based on, but not limited to UCBs. Based on this survey we present an alternative definition of UCBs to improve the CRPD bounds substantially.