Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
A portable global optimizer and linker
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Pipelined processors and worst case execution times
Real-Time Systems
Fixed priority pre-emptive scheduling: an historical perspective
Real-Time Systems - Special issue: history of real-time systems
Static cache simulation and its applications
Static cache simulation and its applications
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications
Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications
Deadline Scheduling for Real-Time Systems: Edf and Related Algorithms
Deadline Scheduling for Real-Time Systems: Edf and Related Algorithms
Cache Behavior Prediction by Abstract Interpretation
SAS '96 Proceedings of the Third International Symposium on Static Analysis
Efficient worst case timing analysis of data caching
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Timing Analysis for Data Caches and Set-Associative Caches
RTAS '97 Proceedings of the 3rd IEEE Real-Time Technology and Applications Symposium (RTAS '97)
Bounding Loop Iterations for Timing Analysis
RTAS '98 Proceedings of the Fourth IEEE Real-Time Technology and Applications Symposium
Worst case timing analysis of RISC processors: R3000/R3010 case study
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Combining Abstract Interpretation and ILP for Microarchitecture Modelling and Program Path Analysis
RTSS '98 Proceedings of the IEEE Real-Time Systems Symposium
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
Experimental Evaluation of Code Properties for WCET Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
FAST: Frequency-Aware Static Timing Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
System-Level Performance Analysis in SystemC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Measuring the cache interference cost in preemptive real-time systems
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Adaptive code unloading for resource-constrained JVMs
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
A time-predictable execution mode for superscalar pipelines with instruction prescheduling
Proceedings of the 2nd conference on Computing frontiers
Improving WCET by applying a WC code-positioning optimization
ACM Transactions on Architecture and Code Optimization (TACO)
FAST: Frequency-aware static timing analysis
ACM Transactions on Embedded Computing Systems (TECS)
Improving WCET by applying worst-case path optimizations
Real-Time Systems
Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison
Proceedings of the conference on Design, automation and test in Europe
Scalable precision cache analysis for real-time software
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
An improved approach for set-associative instruction cache partial analysis
Proceedings of the 2008 ACM symposium on Applied computing
Worst-case execution time analysis of security policies for deeply embedded real-time systems
ACM SIGBED Review - Special issue on the RTSS forum on deeply embedded real-time computing
Cache modeling in probabilistic execution time analysis
Proceedings of the 45th annual Design Automation Conference
Leakage-Aware Energy Efficient Scheduling for Fixed-Priority Tasks with Preemption Thresholds
ADMA '08 Proceedings of the 4th international conference on Advanced Data Mining and Applications
Push-assisted migration of real-time tasks in multi-core processors
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Implementing time-predictable load and store operations
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Time-based intrusion detection in cyber-physical systems
Proceedings of the 1st ACM/IEEE International Conference on Cyber-Physical Systems
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Stack distance based worst-case instruction cache performance analysis
Proceedings of the 2011 ACM Symposium on Applied Computing
Cache-related preemption delay via useful cache blocks: Survey and redefinition
Journal of Systems Architecture: the EUROMICRO Journal
WCET analysis of instruction cache hierarchies
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Making DRAM refresh predictable
Real-Time Systems
Instruction Cache Locking for Embedded Systems using Probability Profile
Journal of Signal Processing Systems
Shared hardware data structures for hard real-time systems
Proceedings of the tenth ACM international conference on Embedded software
PDPA: period driven task and cache partitioning algorithm for multi-core systems
Proceedings of the 20th International Conference on Real-Time and Network Systems
Cache persistence analysis: Theory and practice
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Probabilistic timing analysis on conventional cache designs
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 21st International conference on Real-Time Networks and Systems
Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
WCET analysis with MRU cache: Challenging LRU for predictability
ACM Transactions on Embedded Computing Systems (TECS)
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This paper contributes a comprehensivestudy of a framework to bound worst-case instruction cache performancefor caches with arbitrary levels of associativity. The frameworkis formally introduced, operationally described and its correctnessis shown. Results of incorporating instruction cache predictionswithin pipeline simulation show that timing predictions for set-associativecaches remain just as tight as predictions for direct-mappedcaches. The low cache simulation overhead allows interactiveuse of the analysis tool and scales well with increasing associativity. The approach taken is based on a data-flow specificationof the problem and provides another step toward worst-case executiontime prediction of contemporary architectures and its use inschedulability analysis for hard real-time systems.