Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
A Case for Direct-Mapped Caches
Computer
A portable global optimizer and linker
PLDI '88 Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation
Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Calculating the maximum, execution time of real-time programs
Real-Time Systems
Predicting program execution times by analyzing static and dynamic program paths
Real-Time Systems - Special issue: Real-time languages and language-level timing tools and analysis
Avoiding conditional branches by code replication
PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
Supporting user-friendly analysis of timing constraints
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Static cache simulation and its applications
Static cache simulation and its applications
Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Efficient worst case timing analysis of data caching
RTAS '96 Proceedings of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS '96)
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Fast instruction cache analysis via static cache simulation
SS '95 Proceedings of the 28th Annual Simulation Symposium
Timing Analysis for Data and Wrap-Around Fill Caches
Real-Time Systems
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Supporting Timing Analysis by Automatic Bounding of LoopIterations
Real-Time Systems - Special issue on worst-case execution-time analysis
Symbolic Cache Analysis for Real-Time Systems
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
Variability in the execution of multimedia applications and implications for architecture
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Interval-Based Analysis of Software Processes
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Associative caches in formal software timing analysis
Proceedings of the 39th annual Design Automation Conference
Automatic detection and exploitation of branch constraints for timing analysis
IEEE Transactions on Software Engineering
Processor Pipelines and Their Properties for Static WCET Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
LCTES '00 Proceedings of the ACM SIGPLAN Workshop on Languages, Compilers, and Tools for Embedded Systems
Pipeline Modeling for Timing Analysis
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
Accurate timing analysis by modeling caches, speculation and their interaction
Proceedings of the 40th annual Design Automation Conference
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
The estimation of the WCET in super-scalar real-time system
Real-time system security
Clustered calculation of worst-case execution times
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Experimental Evaluation of Code Properties for WCET Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
FAST: Frequency-Aware Static Timing Analysis
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Approximation of the worst-case execution time using structural analysis
Proceedings of the 4th ACM international conference on Embedded software
Modeling control speculation for timing analysis
Real-Time Systems
A flexible tool for visualizing assembly code
Journal of Computing Sciences in Colleges
Clustered Worst-Case Execution-Time Calculation
IEEE Transactions on Computers
Principles of Timing Anomalies in Superscalar Processors
QSIC '05 Proceedings of the Fifth International Conference on Quality Software
Improving WCET by applying a WC code-positioning optimization
ACM Transactions on Architecture and Code Optimization (TACO)
FAST: Frequency-aware static timing analysis
ACM Transactions on Embedded Computing Systems (TECS)
Automated WCET analysis based on program modes
Proceedings of the 2006 international workshop on Automation of software test
Improving WCET by applying worst-case path optimizations
Real-Time Systems
Modeling out-of-order processors for WCET analysis
Real-Time Systems
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Challenges in Relational Learning for Real-Time Systems Applications
ILP '08 Proceedings of the 18th international conference on Inductive Logic Programming
WCET Analysis of Data Dependent, Component Oriented, Embedded Software Systems
Electronic Notes in Theoretical Computer Science (ENTCS)
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Predicated Worst-Case Execution-Time Analysis
Ada-Europe '09 Proceedings of the 14th Ada-Europe International Conference on Reliable Software Technologies
Multicore-aware hybrid code positioning to reduce worst-case execution time
Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
RaPTEX: a resource-focused toolchain for rapid prototyping of embedded communication systems
Proceedings of the 2010 Workshop on Interaction between Compilers and Computer Architecture
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
Time-based intrusion detection in cyber-physical systems
Proceedings of the 1st ACM/IEEE International Conference on Cyber-Physical Systems
Parametric timing analysis and its application to dynamic voltage scaling
ACM Transactions on Embedded Computing Systems (TECS)
Modeling complex flows for worst-case execution time analysis
RTSS'10 Proceedings of the 21st IEEE conference on Real-time systems symposium
OTAWA: an open toolbox for adaptive WCET analysis
SEUS'10 Proceedings of the 8th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Beyond loop bounds: comparing annotation languages for worst-case execution time analysis
Software and Systems Modeling (SoSyM)
Static timing analysis of real-time operating system code
ISoLA'04 Proceedings of the First international conference on Leveraging Applications of Formal Methods
On using locking caches in embedded real-time systems
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Trace acquirement from real-time systems based on WCET analysis
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Static analysis of the worst-case memory performance for irregular codes with indirections
ACM Transactions on Architecture and Code Optimization (TACO)
Data cache organization for accurate timing analysis
Real-Time Systems
Cache persistence analysis: Theory and practice
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Address independent estimation of the boundaries of cache performance
Microprocessors & Microsystems
Hi-index | 14.98 |
Predicting the execution time of code segments in real-time systems is challenging. Most recently designed machines contain pipelines and caches. Pipeline hazards may result in multicycle delays. Instruction or data memory references may not be found in cache and these misses typically require several cycles to resolve. Whether an instruction will stall due to a pipeline hazard or a cache miss depends on the dynamic sequence of previous instructions executed and memory references performed. Furthermore, these penalties are not independent since delays due to pipeline stalls and cache miss penalties may overlap. This paper describes an approach for bounding the worst and best case performance of large code segments on machines that exploit both pipelining and instruction caching. First, a method is used to analyze a program's control flow to statically categorize the caching behavior of each instruction. Next, these categorizations are used in the pipeline analysis of sequences of instructions representing paths within the program. A timing analyzer uses the pipeline path analysis to estimate the worst and best-case execution performance of each loop and function in the program. Finally, a graphical user interface is invoked that allows a user to request timing predictions on portions of the program. The results indicate that the timing analyzer efficiently produces tight predictions of worst and best-case performance for pipelining and instruction caching