Computing Maximum Task Execution Times — A Graph-BasedApproach
Real-Time Systems
Static timing analysis of embedded software
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemptive Scheduling
IEEE Transactions on Computers
False path analysis based on hierarchical control representation
Proceedings of the 11th international symposium on System synthesis
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Real-Time Performance of Sorting Algorithms
Real-Time Systems
Pipeline behavior prediction for superscalar processors by abstract interpretation
Proceedings of the ACM SIGPLAN 1999 workshop on Languages, compilers, and tools for embedded systems
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Timing Analysis for Data and Wrap-Around Fill Caches
Real-Time Systems
Cache Aware Pre-Runtime Scheduling
Real-Time Systems
Cache-Conscious Limited Preemptive Scheduling
Real-Time Systems
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Supporting Timing Analysis by Automatic Bounding of LoopIterations
Real-Time Systems - Special issue on worst-case execution-time analysis
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
Timing Analysis for Instruction Caches
Real-Time Systems - Special issue on worst-case execution-time analysis
OM '01 Proceedings of the 2001 ACM SIGPLAN workshop on Optimization of middleware and distributed systems
Bounding Cache-Related Preemption Delay for Real-Time Systems
IEEE Transactions on Software Engineering
Energy-conserving feedback EDF scheduling for embedded systems with real-time constraints
Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Using variable-MHz microprocessors to efficiently handle uncertainty in real-time systems
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Automatic detection and exploitation of branch constraints for timing analysis
IEEE Transactions on Software Engineering
ILP-Based Interprocedural Path Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Data cache locking for higher program predictability
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
Data Caches in Multitasking Hard Real-Time Systems
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
Compositional static instruction cache simulation
Proceedings of the 2004 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Fast, predictable and low energy memory references through architecture-aware compilation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A computation offloading scheme on handheld devices
Journal of Parallel and Distributed Computing - Special issue on middleware
Scheduling of Soft Real-Time Systems for Context-Aware Applications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Principles of Timing Anomalies in Superscalar Processors
QSIC '05 Proceedings of the Fifth International Conference on Quality Software
Improving WCET by applying a WC code-positioning optimization
ACM Transactions on Architecture and Code Optimization (TACO)
Worst case execution time analysis for synthesized hardware
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A theory for execution-time derivation in real-time programs
Theoretical Computer Science - Quantitative aspects of programming languages (QAPL 2004)
WCET analysis for a Java processor
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
Timing analysis for preemptive multitasking real-time systems with caches
ACM Transactions on Embedded Computing Systems (TECS)
Data cache locking for tight timing calculations
ACM Transactions on Embedded Computing Systems (TECS)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
An improved approach for set-associative instruction cache partial analysis
Proceedings of the 2008 ACM symposium on Applied computing
Exploiting stack distance to estimate worst-case data cache performance
Proceedings of the 2009 ACM symposium on Applied Computing
Predicated Worst-Case Execution-Time Analysis
Ada-Europe '09 Proceedings of the 14th Ada-Europe International Conference on Reliable Software Technologies
Worst-case execution times for a purely functional language
IFL'06 Proceedings of the 18th international conference on Implementation and application of functional languages
Worst-case execution time analysis for a Java processor
Software—Practice & Experience
A useful bounded resource functional language
SOFSEM'08 Proceedings of the 34th conference on Current trends in theory and practice of computer science
Using NAND flash memory for executing large volume real-time programs in automotive embedded systems
EMSOFT '10 Proceedings of the tenth ACM international conference on Embedded software
Protected hard real-time: the next frontier
Proceedings of the Second Asia-Pacific Workshop on Systems
Improving interrupt response time in a verifiable protected microkernel
Proceedings of the 7th ACM european conference on Computer Systems
On abstractions for timing analysis in the K framework
FOPARA'11 Proceedings of the Second international conference on Foundational and Practical Aspects of Resource Analysis
The WCET analysis tool calcwcet167
ISoLA'12 Proceedings of the 5th international conference on Leveraging Applications of Formal Methods, Verification and Validation: applications and case studies - Volume Part II
Comprehensive formal verification of an OS microkernel
ACM Transactions on Computer Systems (TOCS)
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Real-time systems are characterized by the presence of timing constraints in which a task must be completed within a specific amount of time. This paper examines the problem of determining the bound on the worst case execution time (WCET) of a given program on a given processor There are two important issues in solving this problem: (i) program path analysis, which determines what sequence of instructions will be executed in the worst case, and (ii) microarchitecture modeling, which models the hardware system and determines the WCET of a known sequence of instructions. To obtain a tight estimate on the bound both these issues must be addressed accurately and efficiently. The latter is becoming difficult to model for modern processors due to the presence of pipelined instruction execution units and cached memory systems. Because of the complexity of the problem, all existing methods that we know of focus only on one of above issues. This limits the accuracy of the estimated bound and the size of the program that can be analyzed. We present a more effective solution that addresses both issues and uses an integer linear programming formulation to solve the problem. This solution is implemented in the program cinderella which currently targets the Intel i960KB processor and we present some experimental results of using this tool.