Algorithms
On satisfying timing constraints in hard-real-time systems
SIGSOFT '91 Proceedings of the conference on Software for citical systems
Pipelined processors and worst case execution times
Real-Time Systems
Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Advanced compiler design and implementation
Advanced compiler design and implementation
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Guest Editorial: A Review of Worst-Case Execution-TimeAnalysis
Real-Time Systems - Special issue on worst-case execution-time analysis
Exploiting scratch-pad memory using Presburger formulas
Proceedings of the 14th international symposium on Systems synthesis
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Reducing energy consumption by dynamic copying of instructions onto onchip memory
Proceedings of the 15th international symposium on System Synthesis
An optimal memory allocation scheme for scratch-pad-based embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Scratchpad memory: design alternative for cache on-chip memory in embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
Worst case timing analysis of RISC processors: R3000/R3010 case study
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Efficient microarchitecture modeling and path analysis for real-time software
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Proceedings of the conference on Design, automation and test in Europe
Cache-Aware Scratchpad Allocation Algorithm
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example
IEEE Computer Architecture Letters
Data partitioning for maximal scratchpad usage
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Shared Scratch-Pad Memory Space Management
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Reducing off-chip memory access via stream-conscious tiling on multimedia applications
International Journal of Parallel Programming
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Scratchpad allocation for concurrent embedded software
ACM Transactions on Programming Languages and Systems (TOPLAS)
Reducing memory space consumption through dataflow analysis
Computer Languages, Systems and Structures
Dynamic data type optimization and memory assignment methodologies
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Efficient scratchpad allocation algorithms for energy constrained embedded systems
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
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The design of future high-performance embedded systems is hampered by two problems: First, the required hardware needs more energy than is available from batteries. Second, current cache-based approaches for bridging the increasing speed gap between processors and memories cannot guarantee predictable real-time behavior. A contribution to solving both problems is made in this paper which describes a comprehensive set of algorithms that can be applied at design time in order to maximally exploit scratch pad memories (SPMs). We show that both the energy consumption as well as the computed worst case execution time (WCET) can be reduced by up to to 80% and 48%, respectively, by establishing a strong link between the memory architecture and the compiler.