Real-time Euclid: a language for reliable real-time systems
IEEE Transactions on Software Engineering - Special issue on reliability and safety in real-time process control
The 80960 microprocessor architecture
The 80960 microprocessor architecture
Reasoning About Time in Higher-Level Language Software
IEEE Transactions on Software Engineering
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A task-level hierarchical memory model for system synthesis of multiprocessors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Code generation for core processors
DAC '97 Proceedings of the 34th annual Design Automation Conference
Performance analysis of a system of communicating processes
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Embedded program timing analysis based on path clustering and architecture classification
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Memory data organization for improved cache performance in embedded processor applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code placement techniques for cache miss rate reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A tool for performance estimation of networked embedded end-systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Hardware/software co-synthesis with memory hierarchies
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
AsaP—a framework for evaluating run-time schedulers in embedded multimedia end-systems
MULTIMEDIA '98 Proceedings of the sixth ACM international conference on Multimedia
Bounding Pipeline and Instruction Cache Performance
IEEE Transactions on Computers
Power conscious fixed priority scheduling for hard real-time systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic Cache Analysis for Real-Time Systems
Real-Time Systems - Special issue on worst-case execution-time analysis
WCET Analysis of Superscalar Processors Using SimulationWith Coloured Petri Nets
Real-Time Systems - Special issue on worst-case execution-time analysis
Battery-aware static scheduling for distributed real-time embedded systems
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 14th international symposium on Systems synthesis
Hardware/software co-synthesis with memory hierarchies
Readings in hardware/software co-design
ILP-Based Interprocedural Path Analysis
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Size-Constrained Code Placement for Cache Miss Rate Reduction
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Memory Organization for Improved Data Cache Performance in Embedded Processors
ISSS '96 Proceedings of the 9th international symposium on System synthesis
Iterative schedule optimization for voltage scalable distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Retargetable profiling for rapid, early system-level design space exploration
Proceedings of the 41st annual Design Automation Conference
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fast, predictable and low energy memory references through architecture-aware compilation
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Accurate software performance estimation using domain classification and neural networks
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A time-predictable execution mode for superscalar pipelines with instruction prescheduling
Proceedings of the 2nd conference on Computing frontiers
Multi-metric and multi-entity characterization of applications for early system design exploration
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
System-level performance/power analysis for platform-based design of multimedia applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
SoCDAL: System-on-chip design AcceLerator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Exploiting stack distance to estimate worst-case data cache performance
Proceedings of the 2009 ACM symposium on Applied Computing
The RACECAR heuristic for automatic function specialization on multi-core heterogeneous systems
Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
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Embedded systems generally interact with the outside world. Thus, some real-time constraints may be imposed on the system design. Verification of these constraints requires computing a tight upper bound on the worst case execution time (WCET) of a hardware/software system. The problem of bounding WCET is particularly difficult on modern processors, which use cache-based memory systems that vary memory access time significantly. This must be accurately modeled in order to tightly bound WCET. Existing approaches either search all possible program paths, an intractable problem, or they use pessimistic assumptions to limit the search space. In this paper we present a far more effective and accurate method for modeling instruction cache activity and computing a tight bound on WCET. It is implemented in the program \texttt{cinderella}. We present some preliminary results of using this tool on sample embedded programs.