A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning
EURO-DAC '94 Proceedings of the conference on European design automation
Communication synthesis for distributed embedded systems
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Performance estimation of embedded software with instruction cache modeling
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An architectural co-synthesis algorithm for distributed, embedded computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural exploration and optimization of local memory in embedded systems
ISSS '97 Proceedings of the 10th international symposium on System synthesis
A task-level hierarchical memory model for system synthesis of multiprocessors
DAC '97 Proceedings of the 34th annual Design Automation Conference
COSYN: hardware-software co-synthesis of embedded systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
System-level exploration with SpecSyn
DAC '98 Proceedings of the 35th annual Design Automation Conference
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Hardware/software co-synthesis with memory hierarchies
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
System level memory optimization for hardware-software co-design
Readings in hardware/software co-design
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Hierarchical Scheduling and Allocation of Multirate Systems on Heterogeneous Multiprocessors
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Process Partitioning for Distributed Embedded Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
Analysis of cache-related preemption delay in fixed-priority preemptive scheduling
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Size-Constrained Code Placement for Cache Miss Rate Reduction
ISSS '96 Proceedings of the 9th international symposium on System synthesis
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This paper introduces the first hardware/software co-synthesis algorithm of distributed real-time systems that optimize the memory hierarchy along with the rest of the architecture. Memory hierarchies (caches) are essential for modern embedded cores to obtain high performance. They also represent a significant portion of the cost, size and power consumption of many embedded systems. Our algorithm synthesizes a set of real-time tasks with data dependencies onto a heterogeneous multiprocessor architecture that meets the performance constraints with minimized cost. Unlike previous work in co-synthesis, our algorithm not only synthesizes the hardware and software portions of the applications, but also the memory hierarchies. It chooses cache sizes and allocates tasks to caches as part of co-synthesis. The algorithm is built upon a task-level performance model for memory hierarchies. Experimental results, including examples from the literature and results on real-life examples such as an MPEG-2 encoder, show that our algorithm is efficient, and compared with existing algorithms, it can reduce the overall cost of the synthesized system.