DATE '99 Proceedings of the conference on Design, automation and test in Europe
Hardware/software co-synthesis with memory hierarchies
Readings in hardware/software co-design
A Dependability-Driven System-Level Design Approach for Embedded Systems
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Specification and design considerations for reliable embedded systems
Proceedings of the conference on Design, automation and test in Europe
Progress in autonomous fault recovery of field programmable gate arrays
ACM Computing Surveys (CSUR)
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Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost and reliability goals. In this paper, we address the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. Our algorithm allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions which achieves the required fault coverage without incurring too much overhead. We propose new methods to: 1) perform fault tolerance based task clustering 2) derive the best error recovery topology using a small number of extra processing elements, 3) exploit multi-dimensional assertions, and 4) share assertions to reduce the fault tolerance overhead. Our algorithm can tackle multirate systems commonly found in multimedia applications. Application of the proposed algorithm to several real-life telecom transport system examples shows its efficacy.