Statecharts: A visual formalism for complex systems
Science of Computer Programming
Synthesis of application-specific multiprocessor architectures
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Specification and design of embedded systems
Specification and design of embedded systems
100-hour design cycle: a test case
EURO-DAC '94 Proceedings of the conference on European design automation
Incremental hardware estimation during hardware/software functional partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Procedure exlining: a transformation for improved system and behavioral synthesis
ISSS '95 Proceedings of the 8th international symposium on System synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
A dynamic design estimation and exploration environment
DAC '97 Proceedings of the 34th annual Design Automation Conference
A hardware/software partitioner using a dynamically determined granularity
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Hardware-Software Codesign Methodology for DSP Applications
IEEE Design & Test
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Hardware-Software Cosynthesis for Microcontrollers
IEEE Design & Test
Software estimation using a generic-processor model
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Model Refinement for Hardware-Software Codesign
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Process Partitioning for Distributed Embedded Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware/software co-synthesis with memory hierarchies
Readings in hardware/software co-design
IEEE Transactions on Software Engineering
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
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We present the SpecSyn system-level design environment supp orting the sp ecify-explor e-refine (SER) designparadigm. This thr ee-step appr oach includes precise specification of system functionality, rapid explor ation of numerous system-level design options, and refinement of the specification into one r efle cting the chosen option. A system-level design option c onsists of an allocation of system components like standard and custom processors, and a partitioning of functionality among those components. Focusing on SpecSyn 'sexploration te chniques, we emphasize its two-phase estimation appr oach and highlight experiments using SpecSyn.