Methods for evaluating and covering the design space during early design development

  • Authors:

  • Matthias Gries

  • Affiliations:

  • CAD-Group, Electronics Research Laboratory, University of California at Berkeley, 231 Cory Hall, CA

  • Venue:
  • Integration, the VLSI Journal
  • Year:
  • 2004

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Abstract

This paper gives an overview of methods used for design space exploration (DSE) of microarchitectures and systems. The DSE problem generally considers two orthogonal issues: (I) How can a single design point be evaluated, (II) how can the design space be covered during the exploration process? The latter question arises since an exhaustive exploration oF the design space is usually prohibitive due to the sheer size of the design space. We explain trade-oil's linked to the choice of appropriate evaluation and coverage methods. The designer has to balance the following issues: the accuracy of the evaluation, the time it takes to evaluate one design point (including the implementation of the evaluation model), the precision/granularity of the design space coverage, and, last but not least, the possibilities for automating the exploration process. We also summarize common representations of the design space and compare current system and microarchitecture level design frameworks. This review eases the choice of a decent exploration policy by providing a comprehensive survey and classification of recent related work. It is focused on system-on-a-chip designs, particularly those used for network processors. These systems are heterogeneous in nature using multiple computation, communication, memory, and peripheral resources.