Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search

  • Authors:
  • S. van Haastregt;P. M. W. Knijnenburg

  • Affiliations:
  • LIACS, Leiden University;University of Amsterdam

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe
  • Year:
  • 2007

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Abstract

When designing embedded systems, one needs to make decisions concerning the different components that will be included in a microprocessor. An important issue is the chip area vs. performance trade-off. In this paper we investigate the relationship between chip area and performance for superscalar microprocessors. We investigate the feasibility to obtain a suitable configuration by searching. We show that our approach gives a good configuration after 100 to 150 iterations using a simple random search algorithm. This shows the feasibility of our approach, in particular when more sophisticated search algorithms are employed as we plan in future work.