Automatic and efficient evaluation of memory hierarchies for embedded systems
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Efficient design space exploration in PICO
CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems
ShiftQ: a bufferred interconnect for custom loop accelerators
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
Journal of VLSI Signal Processing Systems
Automatic Architectural Synthesis of VLIW and EPIC Processors
Proceedings of the 12th international symposium on System synthesis
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
Proceedings of the 40th annual Design Automation Conference
Lattice-based memory allocation
Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
IEEE Transactions on Computers
System Design Using Kahn Process Networks: The Compaan/Laura Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 1
RTL Processor Synthesis for Architecture Exploration and Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 3
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Dynamic Platform Management for Configurable Platform-Based System-on-Chips
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Dual-pipeline heterogeneous ASIP design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Translating affine nested-loop programs to process networks
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations
IEEE Transactions on Computers
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
Journal of VLSI Signal Processing Systems
New Complexity Results on Array Contraction and Related Problems
Journal of VLSI Signal Processing Systems
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Misleading Architecting Tradeoffs
Computer
Lattice-Based Memory Allocation
IEEE Transactions on Computers
Optimizing Compiler for the CELL Processor
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques
A quantitative study and estimation models for extensible instructions in embedded processors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Efficient design space exploration of high performance embedded out-of-order processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Customization of application specific heterogeneous multi-pipeline processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Engineering changes in field modifiable architectures
Formal methods and models for system design
Application specific forwarding network and instruction encoding for multi-pipe ASIPs
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Automated design of application specific superscalar processors: an analytical approach
Proceedings of the 34th annual international symposium on Computer architecture
Proceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems
Proceedings of the conference on Design, automation and test in Europe
Automatic cache tuning for energy-efficiency using local regression modeling
Proceedings of the 44th annual Design Automation Conference
Mapping streaming architectures on reconfigurable platforms
ACM SIGARCH Computer Architecture News - Special issue on the 2006 reconfigurable and adaptive architecture workshop
Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing complexity of multiobjective design space exploration in VLIW-based embedded systems
ACM Transactions on Architecture and Code Optimization (TACO)
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Synthesis of reconfigurable high-performance multicore systems
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
ACM Transactions on Architecture and Code Optimization (TACO)
Design of a real-time face detection parallel architecture using high-level synthesis
EURASIP Journal on Embedded Systems - Special issue on design and architectures for signal and image processing
Fast and robust face detection on a parallel optimized architecture implemented on FPGA
IEEE Transactions on Circuits and Systems for Video Technology
Compilers, architectures and synthesis for embedded computing: retrospect and prospect
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
Impact of high-level transformations within the ROCCC framework
ACM Transactions on Architecture and Code Optimization (TACO)
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Microprocessors & Microsystems
Proceedings of the 38th annual international symposium on Computer architecture
Automatic FIR filter generation for FPGAs
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
FPGA-specific synthesis of loop-nests with pipelined computational cores
Microprocessors & Microsystems
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
HEAP: A Highly Efficient Adaptive multi-Processor framework
Microprocessors & Microsystems
| Hi-index | 4.11 |
The PICO (program in, chip out) project is a long-range HP Labs research effort that aims to automate the design of optimized, application-specific computing systemsýthus enabling the rapid and cost-effective design of custom chips when no adequately specialized, off-the-shelf design is available. PICO research takes a systematic approach to the hierarchical design of complex systems and advances technologies for automatically designing custom nonprogrammable accelerators and VLIW processors. While skeptics often assume that automated design must emulate human designers who invent newsolutions to problems, PICO's approach is to automatically pick the most suitable designs from a well-engineered space of designs. Such automation of embedded computer design promises an era of yetmore growth in the number and variety of innovative smart products by lowering the barriers of design time, designer availability, and design cost.