Alpha architecture reference manual
Alpha architecture reference manual
IEEE/ACM Transactions on Networking (TON)
Specification and design of embedded systems
Specification and design of embedded systems
ACM Transactions on Computer Systems (TOCS)
A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
System Design with SystemC
System-level exploration for pareto-optimal configurations in parameterized systems-on-a-chip
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Performance Tradeoffs in Multithreaded Processors
IEEE Transactions on Parallel and Distributed Systems
Embedded Software in Network Processors - Models and Algorithms
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Design and performance of scalable high-performance programmable routers
Design and performance of scalable high-performance programmable routers
CommBench-a telecommunications benchmark for network processors
ISPASS '00 Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design methodology for a modular service-driven network processor architecture
Computer Networks: The International Journal of Computer and Telecommunications Networking - Network processors
Rate analysis for streaming applications with on-chip buffer constraints
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Comparing Analytical Modeling with Simulation for Network Processors: A Case Study
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Efficient Feasibility Analysis for Real-Time Systems with EDF Scheduling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Methods for evaluating and covering the design space during early design development
Integration, the VLSI Journal
Real-time interfaces for interface-based design of real-time systems with fixed priority scheduling
Proceedings of the 5th ACM international conference on Embedded software
Combining simulation and formal methods for system-level performance analysis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
The DISCO network calculator: a toolbox for worst case analysis
valuetools '06 Proceedings of the 1st international conference on Performance evaluation methodolgies and tools
Workload correlations in multi-processor hard real-time systems
Journal of Computer and System Sciences
CyNC: a MATLAB/SimuLink toolbox for network calculus
Proceedings of the 2nd international conference on Performance evaluation methodologies and tools
Protocol offload analysis by simulation
Journal of Systems Architecture: the EUROMICRO Journal
CyNC: A method for real time analysis of systems with cyclic data flows
Journal of Embedded Computing - Best Papers of RTS' 2005
Cache-aware timing analysis of streaming applications
Real-Time Systems
Wired and wireless sensor networks for industrial applications
Microelectronics Journal
Network interfaces for programmable NICs and multicore platforms
Computer Networks: The International Journal of Computer and Telecommunications Networking
Tight performance bounds in the worst-case analysis of feed-forward networks
INFOCOM'10 Proceedings of the 29th conference on Information communications
Dynamic demultiplexing in network calculus-Theory and application
Performance Evaluation
A self-adversarial approach to delay analysis under arbitrary scheduling
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
Journal of Computer Systems, Networks, and Communications
Embedded Systems Design
On the use of greedy shapers in real-time embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Searching for tight performance bounds in feed-forward networks
MMB&DFT'10 Proceedings of the 15th international GI/ITG conference on Measurement, Modelling, and Evaluation of Computing Systems and Dependability and Fault Tolerance
Perspectives on network calculus: no free lunch, but still good value
Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
Perspectives on network calculus: no free lunch, but still good value
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
Arrival and delay curve estimation for SLA calculus
Proceedings of the Winter Simulation Conference
Leveraging bandwidth improvements to web servers through enhanced network interfaces
The Journal of Supercomputing
System performance evaluation by combining RTC and VHDL simulation: A case study on NICs
Journal of Systems Architecture: the EUROMICRO Journal
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The designs of most systems-on-a-chip (SoC) architectures rely on simulation as a means for performance estimation. Such designs usually start with a parameterizable template architecture, and the design space exploration is restricted to identifying the suitable parameters for all the architectural components. However, in the case of heterogeneous SoC architectures such as network processors the design space exploration also involves a combinatorial aspect--which architectural components are to be chosen, how should they be interconnected, task mapping decisions--thereby increasing the design space. Moreover, in the case of network processor architectures there is also an associated uncertainty in terms of the application scenario and the traffic it will be required to process. As a result, simulation is no longer a feasible option for evaluating such architectures in any automated or semi-antomated design space exploration process due to the high simulation times involved. To address this problem, in this paper we hypothesize that the design space exploration for network processors should be separated into multiple stages, each having a different level of abstraction. Further, it would be appropriate to use analytical evaluation frameworks during the initial stages and resort to simulation techniques only when a relatively small set of potential architectures is identified. None of the known performance evaluation methods for network processors have been positioned from this perspective.We show that there are already suitable analytical models for network processor performance evaluation which may be used to support our hypothesis. To this end, we choose a reference system-level model of a network processor architecture and compare its performance evaluation results derived using a known analytical model [Thiele et al., Design space exploration of network processor architectures, in: Proc. 1st Workshop on Network Processors, Cambridge, MA, February 2002; Thiele et al., A framework for evaluating design tradeoffs in packet processing architectures, in: Proc. 39th Design Automation Conference (DAC), New Orleans, USA, ACM Press, 2002] with the results derived by detailed simulation. Based on this comparison, we propose a scheme for the design space exploration of network processor architectures where both analytical performance evaluation techniques and simulation techniques have unique roles to play.