Eliminating receive livelock in an interrupt-driven kernel
ACM Transactions on Computer Systems (TOCS)
Measuring computer performance: a practitioner's guide
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A framework for evaluating design tradeoffs in packet processing architectures
Proceedings of the 39th annual Design Automation Conference
Computer Networks
A PCI bus simulation framework and some simulation results on PCI Standard 2.1 latency limitations
Journal of Systems Architecture: the EUROMICRO Journal
Embedded Software in Network Processors - Models and Algorithms
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IEEE Transactions on Computers
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IEEE Micro
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EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
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HOTI '08 Proceedings of the 2008 16th IEEE Symposium on High Performance Interconnects
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Journal of Systems Architecture: the EUROMICRO Journal
HERO: High-speed enhanced routing operation in Ethernet NICs for software routers
Computer Networks: The International Journal of Computer and Telecommunications Networking
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PDP '09 Proceedings of the 2009 17th Euromicro International Conference on Parallel, Distributed and Network-based Processing
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EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
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Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
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ACM SIGOPS Operating Systems Review
HotOS'13 Proceedings of the 13th USENIX conference on Hot topics in operating systems
Improving IPS by network processors
The Journal of Supercomputing
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ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS)
Performance analysis of AADL models using real-time calculus
Monterey'08 Proceedings of the 15th Monterey conference on Foundations of Computer Software: future Trends and Techniques for Development
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Proceedings of the Conference on Design, Automation and Test in Europe
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Analytic models allow the performance evaluation of proposed system changes without requiring complex and expensive detailed simulations. In this paper, Real-Time Calculus (RTC), a high-level analysis technique previously proposed for stream-processing hard real-time systems and frequently used to evaluate trade-offs in packet stream processing architectures, has been applied to analyse the behaviour of network interfaces. Moreover, the simulation of HDL (Hardware Description Language) models has been used to build the RTC descriptions required to analyse the behaviour of these relatively complex systems. As a case study of this proposed combination of Real-Time Calculus and HDL simulation, the prediction of buffer-size requirements and bottlenecks on the Network Interface Card (NIC) of a node receiving Ethernet packets, is also provided. This work intends to increase the efficiency of the performance evaluation of systems by providing real-time guarantees on delays and backlogs that are valid up to a certain level of confidence, as opposed to the hard guarantees commonly derived by formal methods.