Design Tradeoffs for Process Scheduling in Shared Memory Multiprocessor Systems
IEEE Transactions on Software Engineering
Web-Application Development Using the Model/View/Controller Design Pattern
EDOC '01 Proceedings of the 5th IEEE International Conference on Enterprise Distributed Object Computing
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
System performance evaluation by combining RTC and VHDL simulation: A case study on NICs
Journal of Systems Architecture: the EUROMICRO Journal
| Hi-index | 0.00 |
To date, most system-level bus simulation platforms have focused on the functional correctness of individual bus components rather than the full system-level evaluation of multiple components operating simultaneously. In this pa-per, a new scalable system-level bus simulation environ-ment is described which allows for the evaluation of the PCI-X bus and a series of components. This simulation environment takes advantage of the tight integration of timing-accurate simulation of PCI hardware components with software-level functional modeling to create a fast, accurate system. A series of software techniques is used to allow for time step synchronization across multiple bus components and bus recovery following a transaction. A graphical user interface allows designers to add new com-ponents to the system easily, enhancing modularity. The accuracy of the new simulation environment has been vali-dated for a collection of candidate PCI-X systems using an in-circuit PCI-X emulator. The new simulation environment is shown to be accurate to within a percent error of 0.95%, 3.79%, and 2.78% for utilization, efficiency, and band-width, respectively.