The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Modelling run-time arbitration by latency-rate servers in dataflow graphs
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Performance analysis of SoC architectures based on latency-rate servers
Proceedings of the conference on Design, automation and test in Europe
Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration
RTCSA '08 Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Priority-Based Budget Scheduler with Conservative Dataflow Model
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
Worst case delay analysis for memory interference in multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software
RTSS '10 Proceedings of the 2010 31st IEEE Real-Time Systems Symposium
Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems
Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
System performance evaluation by combining RTC and VHDL simulation: A case study on NICs
Journal of Systems Architecture: the EUROMICRO Journal
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The transition towards multi-processor systems with shared resources is challenging for real-time systems, since resource interference between concurrent applications must be bounded using timing analysis. There are two common approaches to this problem: 1) Detailed analysis that models the particular resource and arbiter cycle-accurately to achieve tight bounds. 2) Using temporal abstractions, such as latency-rate (LR) servers, to enable unified analysis for different resources and arbiters using well-known timing analysis frameworks. However, the use of abstraction typically implies reducing the tightness of analysis that may result in over-dimensioned systems, although this pessimism has not been properly investigated. This paper compares the two approaches in terms of worst-case execution time (WCET) of applications sharing an SDRAM memory under Credit-Controlled Static-Priority (CCSP) arbitration. The three main contributions are: 1) A detailed interference analysis of the SDRAM memory and CCSP arbiter. 2) Based on the detailed analysis, two optimizations are proposed to the LR analysis that increase the tightness of its interference bounds. 3) An experimental comparison of the two approaches that quantifies their impact on the WCET of applications from the CHStone benchmark.