Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems
ACM SIGBED Review - Work-in-Progress (WiP) Session of the 23rd Euromicro Conference on Real-Time Systems (ECRTS 2011)
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Run-time power-down strategies for real-time SDRAM memory controllers
Proceedings of the 49th Annual Design Automation Conference
Assessing the suitability of the NGMP multi-core processor in the space domain
Proceedings of the tenth ACM international conference on Embedded software
Memory-centric scheduling for multicore hard real-time systems
Real-Time Systems
On the scalability of time-predictable chip-multiprocessing
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
PRETI: partitioned real-time shared cache for mixed-criticality real-time systems
Proceedings of the 20th International Conference on Real-Time and Network Systems
A hard real-time capable multi-core SMT processor
ACM Transactions on Embedded Computing Systems (TECS)
Bounding SDRAM interference: detailed analysis vs. latency-rate analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Conservative open-page policy for mixed time-criticality memory controllers
Proceedings of the Conference on Design, Automation and Test in Europe
Architecture and optimal configuration of a real-time multi-channel memory controller
Proceedings of the Conference on Design, Automation and Test in Europe
DRAM selection and configuration for real-time mobile systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Memory-map selection for firm real-time SDRAM controllers
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
On-chip ring network designs for hard-real time systems
Proceedings of the 21st International conference on Real-Time Networks and Systems
Impact of resource sharing on performance and performance prediction: a survey
CONCUR'13 Proceedings of the 24th international conference on Concurrency Theory
A reconfigurable real-time SDRAM controller for mixed time-criticality systems
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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Multicore processors (CMPs) represent a good solution to provide the performance required by current and future hard real-time systems. However, it is difficult to compute a tight WCET estimation for CMPs due to interferences that tasks suffer when accessing shared hardware resources. We propose an analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations.