Software-based cache partitioning for real-time applications
Journal of Computer and Software Engineering - Special issue: hardware-software codesign
Compiler support for software-based cache partitioning
LCTES '95 Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers, & tools for real-time systems
Efficient and Precise Cache Behavior Prediction for Real-TimeSystems
Real-Time Systems
Fast and Precise WCET Prediction by Separated Cache andPath Analyses
Real-Time Systems - Special issue on worst-case execution-time analysis
A Modular & Retargetable Framework for Tree-Based WCET Analysis
ECRTS '01 Proceedings of the 13th Euromicro Conference on Real-Time Systems
Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques
Modeling out-of-order processors for WCET analysis
Real-Time Systems
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 34th annual international symposium on Computer architecture
Timing predictability of cache replacement policies
Real-Time Systems
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Exploring locking & partitioning for predictable shared caches on multi-cores
Proceedings of the 45th annual Design Automation Conference
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Proceedings of the 36th annual international symposium on Computer architecture
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Unified Cache Modeling for WCET Analysis and Layout Optimizations
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Timing Analysis of Concurrent Programs Running on Shared Cache Multi-Cores
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
PACT '11 Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
Ubik: efficient cache sharing with strict qos for latency-critical workloads
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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Multithreaded processors, in the context of real-time systems, create the opportunity to mix, on the same hardware platform, the execution of a complex real-time workload and the execution of non-critical applications. But resources sharing, inherent to multithreading, hinders the timing analysis of concurrent tasks. Such analyses are critical to real-time tasks which have timing deadlines that must be met and enforced. In this paper, we present the PRETI, Partitioned REal-TIme shared cache scheme, a flexible, low implementation-overhead, shared cache partitioning scheme. PRETI can preclude inter-task conflicts on shared caches, and their pessimistic impact on timing estimates, by allocating private cache space to real-time tasks. Therefore, uniprocessor, i.e. unithread, worst-case execution time (WCET) estimation techniques can be used. The remaining cache space, not reserved for currently running real-time tasks, is shared by all tasks running on the processor, in particular the non-critical ones, enabling high performances for these tasks. Experiments are presented to show that the PRETI cache scheme allows for easing and guaranteeing the schedulability of a set of real-time tasks with tight timing constraints, and enabling high performance for the non-critical tasks.