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IEEE Transactions on Software Engineering
Efficient fair queueing using deficit round robin
SIGCOMM '95 Proceedings of the conference on Applications, technologies, architectures, and protocols for computer communication
Hierarchical packet fair queueing algorithms
IEEE/ACM Transactions on Networking (TON)
Shared-cache clusters in a system with a fully shared memory
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Performance isolation: sharing and isolation in shared-memory multiprocessors
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Resource containers: a new facility for resource management in server systems
OSDI '99 Proceedings of the third symposium on Operating systems design and implementation
Computer architecture: a quantitative approach
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Asim: A Performance Model Framework
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Design Issues and Tradeoffs for Write Buffers
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A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning
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ICCCN '95 Proceedings of the 4th International Conference on Computer Communications and Networks
CQoS: a framework for enabling QoS in shared caches of CMP platforms
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Fair Cache Sharing and Partitioning in a Chip Multiprocessor Architecture
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Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling
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METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors
RTAS '06 Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium
Virtual private machines: user-centric performance
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Architectural support for operating system-driven CMP cache management
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Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
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Operating System Concepts
POWER4 system microarchitecture
IBM Journal of Research and Development
Enforcing performance isolation across virtual machines in xen
Middleware'06 Proceedings of the 7th ACM/IFIP/USENIX international conference on Middleware
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
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Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
A light-weight fairness mechanism for chip multiprocessor memory systems
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FlexDCP: a QoS framework for CMP architectures
ACM SIGOPS Operating Systems Review
Rate-based QoS techniques for cache/memory in CMP platforms
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ACM Transactions on Architecture and Code Optimization (TACO)
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CCGRID '09 Proceedings of the 2009 9th IEEE/ACM International Symposium on Cluster Computing and the Grid
VM3: Measuring, modeling and managing VM shared resources
Computer Networks: The International Journal of Computer and Telecommunications Networking
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Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Coordinated control of multiple prefetchers in multi-core systems
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
SHARP control: controlled shared cache management in chip multiprocessors
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
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Proceedings of the 8th annual IEEE/ACM international symposium on Code generation and optimization
PIRATE: QoS and performance management in CMP architectures
ACM SIGMETRICS Performance Evaluation Review
Proceedings of the Workshop on Binary Instrumentation and Applications
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Proceedings of the 24th ACM International Conference on Supercomputing
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Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
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ACM Transactions on Architecture and Code Optimization (TACO)
LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
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Proceedings of the 6th International Conference on High Performance and Embedded Architectures and Compilers
Replacement policies for shared caches on symmetric multicores: a programmer-centric point of view
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Adaptive timekeeping replacement: Fine-grained capacity management for shared CMP caches
ACM Transactions on Architecture and Code Optimization (TACO)
CoQoS: Coordinating QoS-aware shared resources in NoC-based SoCs
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FeatherWeight: low-cost optical arbitration with QoS support
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PACMan: prefetch-aware cache management for high performance caching
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A high performance adaptive miss handling architecture for chip multiprocessors
Transactions on High-Performance Embedded Architectures and Compilers IV
DIEF: an accurate interference feedback mechanism for chip multiprocessor memory systems
HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
Topology-Aware quality-of-service support in highly integrated chip multiprocessors
ISCA'10 Proceedings of the 2010 international conference on Computer Architecture
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Survey of scheduling techniques for addressing shared resources in multicore processors
ACM Computing Surveys (CSUR)
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CONCUR'13 Proceedings of the 24th international conference on Concurrency Theory
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The Journal of Supercomputing
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Virtual Private Machines (VPM) provide a framework for Quality of Service (QoS) in CMP-based computer systems. VPMs incorporate microarchitecture mechanisms that allow shares of hardware resources to be allocated to executing threads, thus providing applications with an upper bound on execution time regardless of other thread activity. Virtual Private Caches (VPCs) are an important element of VPMs. VPC hardware consists of two major components: the VPC Arbiter, which manages shared cache bandwidth, and the VPC Capacity Manager, which manages the cache storage. Both the VPC Arbiter and VPC Capacity Manager provide minimum service guarantees that, when combined, achieve QoS for the cache subsystem. Simulation-based evaluation shows that conventional cache bandwidth management policies allow concurrently executing threads to affect each other significantly in an uncontrollable manner. The evaluation targets cache bandwidth because the effects of cache capacity sharing have been studied elsewhere. In contrast with the conventional policies, the VPC Arbiter meets its QoS performance objectives on all workloads studied and over a range of allocated bandwidth levels. The VPC Arbiter’s fairness policy, which distributes leftover bandwidth, mitigates the effects of cache preemption latencies, thus ensuring threads a high-degree of performance isolation. Furthermore, the VPC Arbiter eliminates negative bandwidth interference which can improve aggregate throughput and resource utilization.