Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Proceedings of the 18th annual international conference on Supercomputing
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Architectural support for operating system-driven CMP cache management
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 34th annual international symposium on Computer architecture
QoS policies and architecture for cache/memory in CMP platforms
Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Evaluating design tradeoffs in on-chip power management for CMPs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Rate-based QoS techniques for cache/memory in CMP platforms
Proceedings of the 23rd international conference on Supercomputing
Measuring interference between live datacenter applications
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Holistic run-time parallelism management for time and energy efficiency
Proceedings of the 27th international ACM conference on International conference on supercomputing
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As new multi-threaded usage models such as virtualization and consolidation take advantage of multiple cores in CMP architectures, the impact of shared resource contention between VMs and user-level applications introduces Quality of Service(QoS) concerns and challenges. QoS-aware management of these shared platform resources is therefore becoming increasingly important. Various QoS schemes for resource management have been recently proposed, but most of these prior efforts have been focused on controlling individual resource allocation based on priority information passed down from the OS or Hypervisor to system resources. The complexity of this approach increases when multiple levels of resources are associated with an application's performance and power consumption. In this paper we employ simpler rate-based QoS mechanisms which control the execution rate of competing applications. To enable differentiation between simultaneously running applications' performance and power consumption, these rate mechanisms need to dynamically adjust the execution of application. Our proposed PI-RATE architecture introduces a control-theoretic approach to dynamically adjust the execution rate of each application based on the QoS target and monitored resource utilization. We evaluate three modes of PI-RATE architecture - cache QoS targets, performance QoS targets and power QoS targets - to show that the PI-RATE architecture is flexible and effective at enabling QoS in a CMP platform.