The TLB slice—a low-cost high-speed address translation mechanism
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
System architecture evaluation using modular performance analysis: a case study
International Journal on Software Tools for Technology Transfer (STTT)
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Proceedings of the 34th annual international symposium on Computer architecture
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Timing predictability of cache replacement policies
Real-Time Systems
CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms
PACT '07 Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Exploring locking & partitioning for predictable shared caches on multi-cores
Proceedings of the 45th annual Design Automation Conference
Towards practical page coloring-based multicore cache management
Proceedings of the 4th ACM European conference on Computer systems
PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches
Proceedings of the 36th annual international symposium on Computer architecture
Cache-aware scheduling and analysis for multicores
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems
IEEE Transactions on Computers
Timing Analysis for TDMA Arbitration in Resource Sharing Systems
RTAS '10 Proceedings of the 2010 16th IEEE Real-Time and Embedded Technology and Applications Symposium
Worst case delay analysis for memory interference in multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters
RTAS '11 Proceedings of the 2011 17th IEEE Real-Time and Embedded Technology and Applications Symposium
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Deterministic execution model on COTS hardware
ARCS'12 Proceedings of the 25th international conference on Architecture of Computing Systems
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
A calculus for network delay. I. Network elements in isolation
IEEE Transactions on Information Theory
Leveraging Multi-core Computing Architectures in Avionics
EDCC '12 Proceedings of the 2012 Ninth European Dependable Computing Conference
Assessing the suitability of the NGMP multi-core processor in the space domain
Proceedings of the tenth ACM international conference on Embedded software
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Multi-core processors are increasingly considered as execution platforms for embedded systems because of their good performance/ energy ratio. However, the interference on shared resources poses several problems. It may severely reduce the performance of tasks executed on the cores, and it increases the complexity of timing analysis and/or decreases the precision of its results. In this paper, we survey recent work on the impact of shared buses, caches, and other resources on performance and performance prediction.