Impact of PCI-Bus Load on Applications in a PC Architecture
RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Reliable performance analysis of a multicore multithreaded system-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs
ICECCS '09 Proceedings of the 2009 14th IEEE International Conference on Engineering of Complex Computer Systems
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems
IEEE Transactions on Computers
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Worst-case response time analysis of resource access models in multi-core systems
Proceedings of the 47th Design Automation Conference
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Proceedings of the tenth ACM international conference on Embedded software
Assessing the suitability of the NGMP multi-core processor in the space domain
Proceedings of the tenth ACM international conference on Embedded software
Memory-centric scheduling for multicore hard real-time systems
Real-Time Systems
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
Heterogeneous makespan and energy-constrained DAG scheduling
Proceedings of the 2013 workshop on Energy efficient high performance parallel and distributed computing
Bounding SDRAM interference: detailed analysis vs. latency-rate analysis
Proceedings of the Conference on Design, Automation and Test in Europe
Quality of service capabilities for hard real-time applications on multi-core processors
Proceedings of the 21st International conference on Real-Time Networks and Systems
Impact of resource sharing on performance and performance prediction: a survey
CONCUR'13 Proceedings of the 24th international conference on Concurrency Theory
Multi-core composability in the face of memory-bus contention
ACM SIGBED Review
Scheduling of mixed-criticality applications on resource-sharing multicore systems
Proceedings of the Eleventh ACM International Conference on Embedded Software
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
NoC contention analysis using a branch-and-prune algorithm
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Static analysis of multi-core TDMA resource arbitration delays
Real-Time Systems
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Employing COTS components in real-time embedded systems leads to timing challenges. When multiple CPU cores and DMA peripherals run simultaneously, contention for access to main memory can greatly increase a task's WCET. In this paper, we introduce an analysis methodology that computes upper bounds to task delay due to memory contention. First, an arrival curve is derived for each core representing the maximum memory traffic produced by all tasks executed on it. Arrival curves are then combined with a representation of the cache behavior for the task under analysis to generate a delay bound. Based on the computed delay, we show how tasks can be feasibly scheduled according to assigned time slots on each core.