StepNP: A System-Level Exploration Platform for Network Processors
IEEE Design & Test
Worst-case performance analysis of parallel, communicating software processes
Proceedings of the tenth international symposium on Hardware/software codesign
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
CODES+ISSS '04 Proceedings of the international conference on Hardware/Software Codesign and System Synthesis: 2004
Bounding Worst-Case Access Times in Modern Multiprocessor Systems
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Buffer and register allocation for memory space optimization
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Integrated analysis of communicating tasks in MPSoCs
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Improved response time analysis of tasks scheduled under preemptive Round-Robin
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Nomadik®: AMobile Multimedia Application Processor Platform
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
System level performance analysis for real-time automotive multicore and network architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling shared cache and bus in multi-cores for timing analysis
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
Worst-case response time analysis of resource access models in multi-core systems
Proceedings of the 47th Design Automation Conference
Worst case delay analysis for memory interference in multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Learning early-stage platform dimensioning from late-stage timing verification
Proceedings of the Conference on Design, Automation and Test in Europe
Real-time performance analysis of multiprocessor systems with shared memory
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on CAPA'09, Special Section on WHS'09, and Special Section VCPSS' 09
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Formal performance analysis is now regularly applied in the design of distributed embedded systems such as automotive electronics, where it greatly contributes to an improved predictability and platform robustness of complex networked systems. Even though it might be highly beneficial also in MpSoC design, formal performance analysis could not easily be applied so far, because the classical task communication model does not cover processor-memory traffic, which is an integral part of MpSoC timing. Introducing memory accesses as individual transactions under the classical model has shown to be inefficient, and previous approaches work well only under strict orthogonalization of different traffic streams. Recent research has presented extensions of the classical task model and a corresponding analysis that covers performance implications of shared memory traffic. In this paper we present a multithreaded multiprocessors platform and multimedia application. We conduct performance analysis using the new analysis options and specifically benchmark the quality of the available approach. Our experiments show that corner case coverage can now be supplied with a very high accuracy, allowing to quickly investigate architectural alternatives.