Automata for modeling real-time systems
Proceedings of the seventeenth international colloquium on Automata, languages and programming
Model checking and abstraction
ACM Transactions on Programming Languages and Systems (TOPLAS)
Performance analysis of embedded software using implicit path enumeration
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Efficient longest executable path search for programs with complex flows and pipeline effects
CASES '01 Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems
Handbook of Automated Reasoning: Volume 1
Handbook of Automated Reasoning: Volume 1
Integrating the timing analysis of pipelining and instruction caching
RTSS '95 Proceedings of the 16th IEEE Real-Time Systems Symposium
Cache modeling for real-time software: beyond direct mapped instruction caches
RTSS '96 Proceedings of the 17th IEEE Real-Time Systems Symposium
Organizing the Last Line of Defense before Hitting the Memory Wall for CMPs
HPCA '04 Proceedings of the 10th International Symposium on High Performance Computer Architecture
Bounding Worst-Case Access Times in Modern Multiprocessor Systems
ECRTS '05 Proceedings of the 17th Euromicro Conference on Real-Time Systems
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
The temporal logic of programs
SFCS '77 Proceedings of the 18th Annual Symposium on Foundations of Computer Science
Model checking based analysis of end-to-end latency in embedded, real-time systems with clock drifts
Proceedings of the 45th annual Design Automation Conference
WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches
RTAS '08 Proceedings of the 2008 IEEE Real-Time and Embedded Technology and Applications Symposium
Reliable performance analysis of a multicore multithreaded system-on-chip
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Performance Comparison of Techniques on Static Path Analysis of WCET
EUC '08 Proceedings of the 2008 IEEE/IFIP International Conference on Embedded and Ubiquitous Computing - Volume 01
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
RTCSA '09 Proceedings of the 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
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As multicore processors are increasingly adopted in industry, it has become a great challenge to accurately bound the worst-case execution time (WCET) for real-time systems running on multicore chips. This is particularly true because of the inter-thread interferences in accessing shared resources on multicores, such as shared L2 caches, which can significantly affect the performance but are very difficult to be estimated statically. This article proposes an approach to analyzing WCET for multicore processors with shared L2 instruction caches by using a model checking based method. We model each concurrent real-time thread, including the inter-thread cache interferences with a PROMELA process, and derive the WCET by using a binary search algorithm. To reduce the state explosion problem, we propose several techniques for reducing the memory consumption by exploiting domain-specific information. Our experiments indicate that compared to the static analysis technique based on extended ILP (integer linear programming), our approach improves the tightness of WCET estimation by more than 31.1% for the benchmarks we studied. However, due to the inherent complexity of multicore timing analysis and the state explosion problem, the model checking based approach currently can only work with small real-time kernels for dual-core processors.