Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches

Authors:
Wei Zhang;Jun Yan
Affiliations:
-;-
Venue:
RTCSA '09 Proceedings of the 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Year:
2009

Citing 0
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Abstract

In a multi-core processor, different cores typically share the last-level cache, and threads running on different cores may interfere with each other in accessing the shared cache. Therefore, multi-core WCET (Worst-Case Execution Time) analyzer must be able to safely and accurately estimate the worst-case inter-thread cache interferences, which is not supported by current WCET analysis techniques that mainly focus on analyzing uniprocessors. This paper proposes a novel approach to analyzing the worst-case cache interferences and bounding the WCET for threads running on multi-core processors with shared direct-mapped L2 instruction caches. We propose to use an Extended ILP (Integer Linear Programming) to model all the possible inter-thread cache conflicts, based on which we can accurately calculate the worst-case inter-thread cache interferences and derive the WCET. Compared to a recently proposed multi-core static analysis technique based on control flow information alone, this approach improves the tightness of WCET estimation by 13.7% on average.