How not to lie with statistics: the correct way to summarize benchmark results
Communications of the ACM - The MIT Press scientific computation series
Advanced compiler design and implementation
Advanced compiler design and implementation
Systematic design of program analysis frameworks
POPL '79 Proceedings of the 6th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
Compilers: Principles, Techniques, and Tools (2nd Edition)
Compilers: Principles, Techniques, and Tools (2nd Edition)
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
The worst-case execution-time problem—overview of methods and survey of tools
ACM Transactions on Embedded Computing Systems (TECS)
Exploring locking & partitioning for predictable shared caches on multi-cores
Proceedings of the 45th annual Design Automation Conference
Concepts of Switching in the Time-Triggered Network-on-Chip
RTCSA '08 Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
WCET Analysis of Multi-level Non-inclusive Set-Associative Instruction Caches
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
RTCSA '09 Proceedings of the 2009 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Using Bypass to Tighten WCET Estimates for Multi-Core Processors with Shared Instruction Caches
RTSS '09 Proceedings of the 2009 30th IEEE Real-Time Systems Symposium
Resilience analysis: tightening the CRPD bound for set-associative caches
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
Modeling shared cache and bus in multi-cores for timing analysis
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
The aethereal network on chip after ten years: goals, evolution, lessons, and future
Proceedings of the 47th Design Automation Conference
Worst case delay analysis for memory interference in multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
Combining Abstract Interpretation with Model Checking for Timing Analysis of Multicore Software
RTSS '10 Proceedings of the 2010 31st IEEE Real-Time Systems Symposium
Bus-Aware Multicore WCET Analysis through TDMA Offset Bounds
ECRTS '11 Proceedings of the 2011 23rd Euromicro Conference on Real-Time Systems
How to enhance a superscalar processor to provide hard real-time capable in-order SMT
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
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In the development of hard real-time systems, knowledge of the Worst-Case Execution Time (WCET) is needed to guarantee the safety of a system. For single-core systems, static analyses have been developed which are able to derive guaranteed bounds on a program's WCET. Unfortunately, these analyses cannot directly be applied to multi-core scenarios, where the different cores may interfere with each other during the access to shared resources like for example shared buses or memories. For the arbitration of such resources, TDMA arbitration has been shown to exhibit favorable timing predictability properties. In this article, we review and extend a methodology for analyzing access delays for TDMA-arbitrated resources. Formal proofs of the correctness of these methods are given and a thorough experimental evaluation is carried out, where the presented techniques are compared to preexisting ones on an extensive set of real-world benchmarks for different classes of analyzed systems.