CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A method for calculating hard QoS guarantees for Networks-on-Chip
Proceedings of the 2009 International Conference on Computer-Aided Design
Journal of Parallel and Distributed Computing
Designing best effort networks-on-chip to meet hard latency constraints
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
NoC contention analysis using a branch-and-prune algorithm
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Static analysis of multi-core TDMA resource arbitration delays
Real-Time Systems
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This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered System on-Chip (TTSoC) architecture. This includes the design of the switching components that make up the network-on-chip (NoC), as well as the switching algorithm applied in those components. Furthermore, we focus on the implications for the operation of the TTNoC entailed by these design choices, and deal with frequently used scenarios in a NoC, particularly multi-casting. Finally, we present results of a prototype implementation based on FPGA technology.