System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
System-on-chip beyond the nanometer wall
Proceedings of the 40th annual Design Automation Conference
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Design of a Virtual Component Neutral Network-on-Chip Transaction Layer
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
×pipes Lite: A Synthesis Oriented Design Library For Networks on Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Networks on chips for high-end consumer-electronics TV system architectures
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip
Proceedings of the conference on Design, automation and test in Europe
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Concepts of Switching in the Time-Triggered Network-on-Chip
RTCSA '08 Proceedings of the 2008 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications
Application Specific Routing Algorithms for Networks on Chip
IEEE Transactions on Parallel and Distributed Systems
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and implementation of an operating system for composable processor sharing
Microprocessors & Microsystems
A TDM NoC supporting QoS, multicast, and fast connection set-up
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
The CompSOC design flow for virtual execution platforms
Proceedings of the 10th FPGAworld Conference
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A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The diverse requirements, coupled with the IPs being developed by unrelated design teams, lead to multiple communication paradigms, programming models, and interface protocols that the on-chip interconnect must accommodate. Traditionally, on-chip buses offer distributed shared memory communication with established memory-consistency models, but are tightly coupled to a specific interface protocol. On-chip networks, on the other hand, offer layering and interface abstraction, but are centred around point-to-point streaming communication, and do not address issues at the higher layers in the protocol stack, such as memory-consistency models and message-dependent deadlock. In this work we introduce an on-chip interconnect and protocol stack that combines streaming and distributed shared memory communication. The proposed interconnect offers an established memory-consistency model and does not restrict any higher-level protocol dependencies. We present the protocol stack and the architectural blocks and quantify the cost, both on the block level and for a complete SoC. For a multi-processor multi-application SoC with multiple communication paradigms and programming models, our proposed interconnect occupies only 4% of the chip area.