Cache coherency communication cost in a NoC-based MPSoC platform
Proceedings of the 20th annual conference on Integrated circuits and systems design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A tuneable software cache coherence protocol for heterogeneous MPSoCs
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
81.6 GOPS object recognition processor based on a memory-centric NoC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Scalability of relaxed consistency models in NoC based multicore architectures
ACM SIGARCH Computer Architecture News
Exploring memory organization in virtual MP-SoC platforms
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Energy-efficient cache coherence protocol for NoC-based MPSoCs
Proceedings of the 24th symposium on Integrated circuits and systems design
Programming a Multicore Architecture without Coherency and Atomic Operations
Proceedings of Programming Models and Applications on Multicores and Manycores
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The concept of network on chip (NoC) is a recent breakthrough in the system on chip (SoC) design area. A lot of work has been done to define efficient NoC architectures and implementations. In this paper, our goal is twofold. Firstly, we want to outline that the use of a NoC based sharedmemory multiprocessor SoC challenges the application integrator because of the underlying assumptions of software, namely cache coherency and memory consistency. These problems are well known in general purpose shared memory multiprocessors. However, when designing a SoC, we benefit on the one hand from the knowledge of the applications, the much simpler usage of virtual memory, lower interconnect latencies and very high bandwidth at lost cost, but on the other hand we suffer from more tight design constraints (yield, power, predictable performances, ...). Secondly, we define simple and yet attractive solutions -in term of design time and hardware cost- to both problems in the context of application specific multiprocessor SoCs.