Programming a Multicore Architecture without Coherency and Atomic Operations

  • Authors:

  • Jochem H. Rutgers;Marco J. G. Bekooij;Gerard J. M. Smit

  • Affiliations:

  • University of Twente, Department of EEMCS, P.O. Box 217, 7500 AE Enschede, The Netherlands;University of Twente, Department of EEMCS, P.O. Box 217, 7500 AE Enschede, The Netherlands;University of Twente, Department of EEMCS, P.O. Box 217, 7500 AE Enschede, The Netherlands

  • Venue:
  • Proceedings of Programming Models and Applications on Multicores and Manycores
  • Year:
  • 2014

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Abstract

It is hard to reason about the state of a multicore system-on-chip, because operations on memory need multiple cycles to complete, since cores communicate via an interconnect like a network-on-chip. To simplify programming, atomicity is required, by means of atomic read-modify-write (RMW) operations, a strong memory model, and hardware cache coherency. As a result, multicore architectures are very complex, but this stems from the fact that they are designed with an imperative programming paradigm in mind, i.e. based on threads that communicate via shared memory. In this paper, we show the impact on a multicore architecture, when the programming paradigm is changed and a λ-calculus-based (functional) language is used instead. Ordering requirements of memory operations are more relaxed and synchronization is simplified, because λ-calculus does not have a notion of state or memory, and therefore does not impose ordering requirements on the platform. We implemented a functional language for multicores with a weak memory model, without the need of hardware cache coherency, any atomic RMW operation, or mutex---the execution is atomic-free. Experiments show that even on a system with (transparently applied) software cache coherency, execution scales properly up to 32 cores. This shows that concurrent hardware complexity can be reduced by making different choices in the software layers on top.