Scalability of relaxed consistency models in NoC based multicore architectures

Authors:
Abdul Naeem;Xiaowen Chen;Zhonghai Lu;Axel Jantsch
Affiliations:
School of ICT, Royal Institute of Technology (KTH), Stockholm, Sweden;School of ICT, Royal Institute of Technology (KTH), Stockholm, Sweden and Institute of Microelectronics and Microprocessor, School of CS, NUDT, Changsha, China;School of ICT, Royal Institute of Technology (KTH), Stockholm, Sweden;School of ICT, Royal Institute of Technology (KTH), Stockholm, Sweden
Venue:
ACM SIGARCH Computer Architecture News
Year:
2010

Citing 15
Cited 0

Memory consistency models

ACM SIGOPS Operating Systems Review
Memory consistency models for shared-memory multiprocessors

Memory consistency models for shared-memory multiprocessors
Memory consistency and event ordering in scalable shared-memory multiprocessors

ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Shared Memory Consistency Models: A Tutorial

Computer
Networks on Chips: A New SoC Paradigm

Computer
Hardware- and Software-Based Collective Communication on the Quadrics Network

NCA '01 Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA'01)
Networks on chip

Networks on chip
A unified theory of shared memory consistency

Journal of the ACM (JACM)
Challenges in Embedded Memory Design and Test

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
On Cache Coherency and Memory Consistency Issues in NoC Based Shared Memory Multiprocessor SoC Architectures

DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
Larrabee: a many-core x86 architecture for visual computing

ACM SIGGRAPH 2008 papers
Efficiency and scalability of barrier synchronization on NoC based many-core architectures

CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Networks-on-Chips: Theory and Practice

Networks-on-Chips: Theory and Practice
Processor Architecture Design Using 3D Integration Technology

VLSID '10 Proceedings of the 2010 23rd International Conference on VLSI Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper studies realization of relaxed memory consistency models in the network-on-chip based distributed shared memory (DSM) multi-core systems. Within DSM systems, memory consistency is a critical issue since it affects not only the performance but also the correctness of programs. We investigate the scalability of the relaxed consistency models (weak, release consistency) implemented by using transaction counters. Our experimental results compare the average and maximum code, synchronization and data latencies of the two consistency models for various network sizes with regular mesh topologies. The observed latencies rise for both the consistency models as the network size grows. However, the scaling behaviors are different. With the release consistency model these latencies grow significantly slower than with the weak consistency due to better optimization potential by means of overlapping, reordering and program order relaxations. The release consistency improves the performance by 15.6% and 26.5% on average in the code and consistency latencies over the weak consistency model for the specific application, as the system grows from single core to 64 cores. The latency of data transactions grows 2.2 times faster on the average with a weak consistency model than with a release consistency model when the system scales from single core to 64 core