Networks on chip

System-on-chip beyond the nanometer wall

Proceedings of the 40th annual Design Automation Conference

Network-on-Chip Modeling for System-Level Multiprocessor Simulation

RTSS '03 Proceedings of the 24th IEEE International Real-Time Systems Symposium

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Distributed Multimedia System Design: A Holistic Perspective

Proceedings of the conference on Design, automation and test in Europe - Volume 2

Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding

Proceedings of the conference on Design, automation and test in Europe - Volume 3

OCCN: a NoC modeling framework for design exploration

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip

SUNMAP: a tool for automatic topology selection and generation for NoCs

Proceedings of the 41st annual Design Automation Conference

Low-Latency Virtual-Channel Routers for On-Chip Networks

Proceedings of the 31st annual international symposium on Computer architecture

Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

ParIS: a parameterizable interconnect switch for networks-on-chip

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip

IEEE Transactions on Parallel and Distributed Systems

An Application-Specific Design Methodology for STbus Crossbar Generation

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips

Proceedings of the conference on Design, Automation and Test in Europe - Volume 2

A Scalable Parallel SoC Architecture for Network Processors

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design

Key research problems in NoC design: a holistic perspective

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Application-specific network-on-chip architecture customization via long-range link insertion

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh

Proceedings of the conference on Design, automation and test in Europe: Designers' forum

A methodology for mapping multiple use-cases onto networks on chips

Proceedings of the conference on Design, automation and test in Europe: Proceedings

A survey of research and practices of Network-on-chip

ACM Computing Surveys (CSUR)

HIBI Communication Network for System-on-Chip

Journal of VLSI Signal Processing Systems

Computation and communication refinement for multiprocessor SoC design: A system-level perspective

Proceedings of the 41st annual Design Automation Conference

Design space exploration and prototyping for on-chip multimedia applications

Proceedings of the 43rd annual Design Automation Conference

Prediction-based flow control for network-on-chip traffic

Proceedings of the 43rd annual Design Automation Conference

Aspect-oriented design in systemC: implementation and applications

SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design

Bounded arbitration algorithm for QoS-supported on-chip communication

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

The SegBus platform - architecture and communication mechanisms

Journal of Systems Architecture: the EUROMICRO Journal

Application of deterministic and stochastic Petri-Nets for performance modeling of NoC architectures

Journal of Systems Architecture: the EUROMICRO Journal

On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Transaction-Based Communication-Centric Debug

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

Towards Open Network-on-Chip Benchmarks

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

NoC Design and Implementation in 65nm Technology

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC

NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip

A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method

Proceedings of the conference on Design, automation and test in Europe

An evolutionary approach to collective communication scheduling

Proceedings of the 9th annual conference on Genetic and evolutionary computation

Router architecture for high-performance NoCs

Proceedings of the 20th annual conference on Integrated circuits and systems design

A predictive NoC architecture for vision systems dedicated to image analysis

EURASIP Journal on Embedded Systems

Analysis and optimization of prediction-based flow control in networks-on-chip

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Bringing NoCs to 65 nm

IEEE Micro

Power and reliability management of SoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Invited paper: Network-on-Chip design and synthesis outlook

Integration, the VLSI Journal

QoS-supported on-chip communication for multi-processors

International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems

3-D topologies for networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A Design-for-Test Implementation of an Asynchronous Network-on-Chip Architecture and its Associated Test Pattern Generation and Application

NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip

Minimizing virtual channel buffer for routers in on-chip communication architectures

Proceedings of the conference on Design, automation and test in Europe

Design of a HW/SW communication infrastructure for a heterogeneous reconfigurable processor

Proceedings of the conference on Design, automation and test in Europe

Multicast parallel pipeline router architecture for network-on-chip

Proceedings of the conference on Design, automation and test in Europe

Three-dimensional Integrated Circuit Design

Three-dimensional Integrated Circuit Design

MCF: a metamodeling-based component composition framework-composing SystemC IPs for executable system models

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Link-load balance aware mapping and routing for NoC

WSEAS Transactions on Circuits and Systems

Frequent value compression in packet-based NoC architectures

Proceedings of the 2009 Asia and South Pacific Design Automation Conference

SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs

ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems

Networks-on-chip based on dynamic wormhole packet identity mapping management

VLSI Design

Networks-on-chip in emerging interconnect paradigms: Advantages and challenges

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip

Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip

BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip

Statistical physics approaches for network-on-chip traffic characterization

CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Design and management of voltage-frequency island partitioned networks-on-chip

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A networks-on-chip architecture design space exploration - The LIB

Computers and Electrical Engineering

A routing-table-based adaptive and minimal routing scheme on network-on-chip architectures

Computers and Electrical Engineering

Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

An outlook on design technologies for future integrated systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

An asynchronous router with multicast support in NoC

CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems

Local search: is brute-force avoidable?

IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence

A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints

ACM Transactions on Architecture and Code Optimization (TACO)

On a web-graph-based micronetwork architecture for SoCs

International Journal of Computers and Applications

A multi-path routing scheme for torus-based NOCs

International Journal of Computers and Applications

Scalability of relaxed consistency models in NoC based multicore architectures

ACM SIGARCH Computer Architecture News

Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints

Proceedings of the 2010 ACM Symposium on Applied Computing

Power and performance optimization of voltage/frequency island-based networks-on-chip using reconfigurable synchronous/bi-synchronous FIFOs

Proceedings of the 7th ACM international conference on Computing frontiers

Communication-aware face detection using noc architecture

ICVS'08 Proceedings of the 6th international conference on Computer vision systems

Performance prediction of throughput-centric pipelined global interconnects with voltage scaling

Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction

Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

A Low-Latency and Memory-Efficient On-chip Network

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip

Virtual point-to-point connections for NoCs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip

Accurate predictive interconnect modeling for system-level design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs

Proceedings of the 12th annual conference on Genetic and evolutionary computation

Energy efficient mapping and voltage islanding for regular NoC under design constraints

International Journal of High Performance Systems Architecture

Network interface design based on mutual interface definition

International Journal of High Performance Systems Architecture

Supporting distributed shared memory on multi-core network-on-chips using a dual microcoded controller

Proceedings of the Conference on Design, Automation and Test in Europe

Error resilience of intra-die and inter-die communication with 3D Spidergon STNoC

Proceedings of the Conference on Design, Automation and Test in Europe

Workload characterization and its impact on multicore platform design

CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

A methodology for design of unbuffered router microarchitecture for S-mesh NoC

NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing

Embedded network protocols for mobile devices

FMICS'10 Proceedings of the 15th international conference on Formal methods for industrial critical systems

Reducing the associativity and size of step caches in CRCW operation

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing

A generic adaptive path-based routing method for MPSoCs

Journal of Systems Architecture: the EUROMICRO Journal

An analytical approach for network-on-chip performance analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A networks-on-chip emulation/verification framework

International Journal of High Performance Systems Architecture

System design of full HD MVC decoding on mesh-based multicore NoCs

Microprocessors & Microsystems

Performance comparison of some shared memory organizations for 2D mesh-like NOCs

Microprocessors & Microsystems

Scalable network-on-chip architecture for configurable neural networks

Microprocessors & Microsystems

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Network-on-chip router design with buffer-stealing

Proceedings of the 16th Asia and South Pacific Design Automation Conference

Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip

Microprocessors & Microsystems

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

"It's a small world after all": noc performance optimization via long-range link insertion

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Energy-optimized on-chip networks using reconfigurable shortcut paths

ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems

GNLS: a hybrid on-chip communication architecture for SoC designs

International Journal of High Performance Systems Architecture

3D floorplanning of low-power and area-efficient Network-on-Chip architecture

Microprocessors & Microsystems

Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

Spidergon STNoC design flow

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip

A layout for sparse cube-connected-cycles network

Proceedings of the 12th International Conference on Computer Systems and Technologies

Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels

PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation

Service based communication for MPSoC platform-SegBus

Microprocessors & Microsystems

Evolutionary design of group communication schedules for interconnection networks

ISCIS'05 Proceedings of the 20th international conference on Computer and Information Sciences

Evolutionary design of OAB and AAB communication schedules for interconnection networks

EuroGP'06 Proceedings of the 2006 international conference on Applications of Evolutionary Computing

Transaction level modeling in practice: motivation and introduction

Proceedings of the International Conference on Computer-Aided Design

Making-a-stop: A new bufferless routing algorithm for on-chip network

Journal of Parallel and Distributed Computing

Modeling noc architectures by means of deterministic and stochastic petri nets

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation

ESL Design and Verification: A Prescription for Electronic System Level Methodology

ESL Design and Verification: A Prescription for Electronic System Level Methodology

Benefits of selective packet discard in networks-on-chip

ACM Transactions on Architecture and Code Optimization (TACO)

A novel 3D NoC architecture based on De Bruijn graph

Computers and Electrical Engineering

Power consumption and performance analysis of 3D NoCs

ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture

Junction based routing: a scalable technique to support source routing in large NoC platforms

Proceedings of the Fifth International Workshop on Network on Chip Architectures

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis

International Journal of Embedded and Real-Time Communication Systems

Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture

Journal of Computer and System Sciences

Dynamic power management for multidomain system-on-chip platforms: An optimal control approach

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies

Fuzzy-based Adaptive Routing Algorithm for Networks-on-Chip

Journal of Systems Architecture: the EUROMICRO Journal

A fault tolerant NoC architecture using quad-spare mesh topology and dynamic reconfiguration

Journal of Systems Architecture: the EUROMICRO Journal

A development and verification framework for the SegBus platform

Journal of Systems Architecture: the EUROMICRO Journal