Network-on-chip router design with buffer-stealing

Authors:
Wan-Ting Su;Jih-Sheng Shen;Pao-Ann Hsiung
Affiliations:
National Chung Cheng University, Chiayi, Taiwan, ROC;National Chung Cheng University, Chiayi, Taiwan, ROC;National Chung Cheng University, Chiayi, Taiwan, ROC
Venue:
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Year:
2011

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Abstract

Communication in a Network-on-Chip (NoC) can be made more efficient by designing faster routers, using larger buffers, larger number of ports and channels, and adaptive routing, all of which incur significant overheads in hardware costs. As a more economic solution, we try to improve communication efficiency without increasing the buffer size. A Buffer-Stealing (BS) mechanism is proposed, which enables the input channels that have insufficient buffer space to utilize at runtime the unused input buffers from other input channels. Implementation results of the proposed BS design for a 64-bit 5-input-buffer router show a reduction of the average packet transmission latency by up to 10.17% and an increase of the average throughput by up to 23.47%, at an overhead of 22% more hardware resources.