The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Throughput-driven IC communication fabric synthesis
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
PowerHerd: dynamic satisfaction of peak power constraints in interconnection networks
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Communication Architectures for System-on-Chip
Proceedings of the 14th symposium on Integrated circuits and systems design
Networks on chip
Efficient Synthesis of Networks On Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
On-chip networks: A scalable, communication-centric embedded system design paradigm
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
An Interconnect Channel Design Methodology for High Performance Integrated Circuits
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
Multi-objective mapping for mesh-based NoC architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
An architecture and compiler for scalable on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linear Programming based Techniques for Synthesis of Network-on-Chip Architectures
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Application-specific buffer space allocation for networks-on-chip router design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Energy- and performance-aware mapping for regular NoC architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simulation and analysis of network on chip architectures: ring, spidergon and 2D mesh
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Is "Network" the next "Big Idea" in design?
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Application specific NoC design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Computation and communication refinement for multiprocessor SoC design: A system-level perspective
Proceedings of the 41st annual Design Automation Conference
Bounded arbitration algorithm for QoS-supported on-chip communication
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Profile-driven energy reduction in network-on-chips
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Towards Open Network-on-Chip Benchmarks
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Run-time adaptive on-chip communication scheme
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Proceedings of the 18th ACM Great Lakes symposium on VLSI
QoS-supported on-chip communication for multi-processors
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Application mapping for chip multiprocessors
Proceedings of the 45th annual Design Automation Conference
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Zero-efficient buffer design for reliable network-on-chip in tiled chip-multi-processor
Proceedings of the conference on Design, automation and test in Europe
Minimizing virtual channel buffer for routers in on-chip communication architectures
Proceedings of the conference on Design, automation and test in Europe
A Link-Load Balanced Low Energy Mapping and Routing for NoC
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Modeling and Implementation of an Output-Queuing Router for Networks-on-Chips
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Highly-cited ideas in system codesign and synthesis
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Link-load balance aware mapping and routing for NoC
WSEAS Transactions on Circuits and Systems
Long-range dependence and on-chip processor traffic
Microprocessors & Microsystems
A comprehensive power-performance model for NoCs with multi-flit channel buffers
Proceedings of the 23rd international conference on Supercomputing
Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evolutionary IP assignment for efficient NoC-based system design using multi-objective optimization
CEC'09 Proceedings of the Eleventh conference on Congress on Evolutionary Computation
An analytical performance model for the Spidergon NoC with virtual channels
Journal of Systems Architecture: the EUROMICRO Journal
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints
ACM Transactions on Architecture and Code Optimization (TACO)
Low power nanoscale buffer management for network on chip routers
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Efficient mapping of an image processing application for a network-on-chip based implementation
International Journal of High Performance Systems Architecture
Communication modeling of multicast in all-port wormhole-routed NoCs
Journal of Systems and Software
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A fast MPI-based parallel framework for cycle-accurate HDL multi-parametric simulations
International Journal of High Performance Systems Architecture
Quarter Load Threshold (QLT) flow control for wormhole switching in mesh-based Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Comprehensive on-chip traffic generator model for SoC design and synthesis
SpringSim '10 Proceedings of the 2010 Spring Simulation Multiconference
Exploring programming model-driven QoS support for NoC-based platforms
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An analytical model of broadcast in QoS-aware wormhole-routed NoCs
Journal of Systems and Software
State observer controller design for packets flow control in networks-on-chip
The Journal of Supercomputing
Journal of Systems Architecture: the EUROMICRO Journal
A unified design space simulation environment for network-on-chip: fuse-N
International Journal of High Performance Systems Architecture
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip
Microprocessors & Microsystems
Power-aware multi-objective evolutionary optimization for application mapping on NoC platforms
IEA/AIE'10 Proceedings of the 23rd international conference on Industrial engineering and other applications of applied intelligent systems - Volume Part II
Network-on-chip router design with buffer-stealing
Proceedings of the 16th Asia and South Pacific Design Automation Conference
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Expert Systems with Applications: An International Journal
A multi-level design methodology of multistage interconnection network for MPSOCs
International Journal of Computer Applications in Technology
Concurrent hybrid switching for massively parallel systems-on-chip: the CYBER architecture
Proceedings of the 9th conference on Computing Frontiers
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
Performance analysis and comparison of 2×4 network on chip topology
Microprocessors & Microsystems
A multi-objective mapping strategy for application specific emesh network-on-chip (noc)
ICSI'12 Proceedings of the Third international conference on Advances in Swarm Intelligence - Volume Part I
A survey on application mapping strategies for Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Congestion-aware scheduling for NoC-based reconfigurable systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
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Networks-on-Chip (NoCs) have been recently proposed as a promising solution to complex on-chip communication problems. The lack of an unified representation of applications and architectures makes NoC problem formulation and classification both difficult and obscure. To remedy this situation, we provide a general description for NoC architectures and applications and then enumerate several outstanding research problems (denoted by P1-P8) organized under three topics: communication infrastructure synthesis, communication paradigm selection, and application mapping optimization. Far from being exhaustive, the discussed problems are deemed essential for future NoC research.