A Cost and Speed Model for k-ary n-Cube Wormhole Routers
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Compartmental Modeling with Networks
Compartmental Modeling with Networks
Modern Control System Theory
A Delay Model for Router Microarchitectures
IEEE Micro
On-chip traffic modeling and synthesis for MPEG-2 video applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Key research problems in NoC design: a holistic perspective
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe
Congestion-controlled best-effort communication for networks-on-chip
Proceedings of the conference on Design, automation and test in Europe
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Performance analysis and comparison of 2×4 network on chip topology
Microprocessors & Microsystems
An energy-aware online task mapping algorithm in NoC-based system
The Journal of Supercomputing
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Packet-switched networks-on-chips (NoCs) are efficient communication architectures for future multiprocessors system-on-chip (MP-SoC) platforms. However the run-time management of their communication, especially flow control from individual intellectual property (IP) in an NoC which contains large number of IPs, is a challenging task. This paper proposes a state space model for NoC with state observer controller in its feedback path. It is seen that controlling the input and output flow rates alone is not sufficient to stabilize the network, but it is also important to monitor the intermediate flow rates from the on-chip routers. This is possible through a state space model for the NoC. The state observer observes the flow rates from each on-chip router which are then treated as state space variables. These variables can be controlled by the poles placement in the feedback controller. The proposed mathematical model can also observe the required intermediate flow rates which cannot be measured directly (reduced state observer). With these observed states we can attach a state controller. With this controller the network can be stabilized by controlling the flow rates at the intermediate level.