Logical effort: designing for speed on the back of an envelope
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
A Cost and Speed Model for k-ary n-Cube Wormhole Routers
IEEE Transactions on Parallel and Distributed Systems
Digital systems engineering
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Spider: A High-Speed Network Interconnect
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
Performance Evaluation of Adaptive Routing Algorithms for k-ary-n-cubes
PCRCW '94 Proceedings of the First International Workshop on Parallel Computer Routing and Communication
A Delay Model and Speculative Architecture for Pipelined Routers
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources
IEEE Transactions on Parallel and Distributed Systems
GOAL: a load-balanced adaptive routing algorithm for torus networks
Proceedings of the 30th annual international symposium on Computer architecture
Evaluation of queue designs for true fully adaptive routers
Journal of Parallel and Distributed Computing
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Microarchitecture of a High-Radix Router
Proceedings of the 32nd annual international symposium on Computer Architecture
Performance analysis of a QoS capable cluster interconnect
Performance Evaluation - Performance modelling and evaluation of high-performance parallel and distributed systems
Application-specific buffer space allocation for networks-on-chip router design
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Prediction-based flow control for network-on-chip traffic
Proceedings of the 43rd annual Design Automation Conference
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Interconnect design considerations for large NUCA caches
Proceedings of the 34th annual international symposium on Computer architecture
A Study of NoC Exit Strategies
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Layered switching for networks on chip
Proceedings of the 44th annual Design Automation Conference
The Effects of Simulated Inertia and Force Prediction on Delayed Telepresence
Presence: Teleoperators and Virtual Environments
Analysis and optimization of prediction-based flow control in networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Advancing supercomputer performance through interconnection topology synthesis
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Reliability aware NoC router architecture using input channel buffer sharing
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Breaking adaptive multicast deadlock by virtual channel address/data FIFO decoupling
Proceedings of the 2nd International Workshop on Network on Chip Architectures
The connection-then-credit flow control protocol for heterogeneous multicore systems-on-chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Virtual channels vs. multiple physical networks: a comparative analysis
Proceedings of the 47th Design Automation Conference
Feedback control for providing QoS in NoC based multicores
Proceedings of the Conference on Design, Automation and Test in Europe
Performance modeling of n-dimensional mesh networks
Performance Evaluation
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
State observer controller design for packets flow control in networks-on-chip
The Journal of Supercomputing
A latency simulator for many-core systems
Proceedings of the 44th Annual Simulation Symposium
3D NOC for many-core processors
Microelectronics Journal
Network on chip for parallel DSP architectures
ICESS'05 Proceedings of the Second international conference on Embedded Software and Systems
Networks on chips: structure and design methodologies
Journal of Electrical and Computer Engineering - Special issue on Networks-on-Chip: Architectures, Design Methodologies, and Case Studies
TMNOC: a case of HTM and NoC co-design for increased energy efficiency and concurrency
Proceedings of the 21st international conference on Parallel architectures and compilation techniques
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Given router parameters, this delay model prescribes realistic pipelines, enabling router architects to optimize network performance before beginning actual detailed design.