Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
Journal of the ACM (JACM)
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
High-performance bidirectional repeaters
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Toward achieving energy efficiency in presence of deep submicron noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Energy efficient fixed-priority scheduling for real-time systems on variable voltage processors
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 14th international symposium on Systems synthesis
Task scheduling and voltage selection for energy minimization
Proceedings of the 39th annual Design Automation Conference
Real-Time Systems
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
A Delay Model for Router Microarchitectures
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
A Genetic Algorithm for Multiprocessor Scheduling
IEEE Transactions on Parallel and Distributed Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Energy efficient CMOS microprocessor design
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
A Synthesis Method for Fault-tolerant and Flexible Multipath Routing Protocols
ICECCS '97 Proceedings of the Third IEEE International Conference on Engineering of Complex Computer Systems
Energy-Efficient Mapping and Scheduling for DVS Enabled Distributed Embedded Systems
Proceedings of the conference on Design, automation and test in Europe
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Iterative schedule optimization for voltage scalable distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
Quality-of-service and error control techniques for network-on-chip architectures
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
Communication-Aware Task Scheduling and Voltage Selection for Total Systems Energy Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A low latency router supporting adaptivity for on-chip interconnects
Proceedings of the 42nd annual Design Automation Conference
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
ISPAN '05 Proceedings of the 8th International Symposium on Parallel Architectures,Algorithms and Networks
A Virtual Channel Network-on-Chip for GT and BE traffic
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Improving routing efficiency for network-on-chip through contention-aware input selection
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Towards on-chip fault-tolerant communication
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Efficient link capacity and QoS design for network-on-chip
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Exploring Fault-Tolerant Network-on-Chip Architectures
DSN '06 Proceedings of the International Conference on Dependable Systems and Networks
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
Proceedings of the 43rd annual Design Automation Conference
Ant colony based routing architecture for minimizing hot spots in NOCs
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
A Fault tolerant mechanism for handling Permanent and Transient Failures in a Network on Chip
ITNG '07 Proceedings of the International Conference on Information Technology
Architecture of the Scalable Communications Core
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Fully Adaptive Fault-Tolerant Routing Algorithm for Network-on-Chip Architectures
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Neighbors-on-Path: A New Selection Strategy for On-Chip Networks
ESTMED '06 Proceedings of the 2006 IEEE/ACM/IFIP Workshop on Embedded Systems for Real Time Multimedia
ETAHM: an energy-aware task allocation algorithm for heterogeneous multiprocessor
Proceedings of the 45th annual Design Automation Conference
Forecasting-Based Dynamic Virtual Channels Allocation for Power Optimization of Network-on-Chips
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Quality-of-service and error control techniques for mesh-based network-on-chip architectures
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
A Load-Balanced Routing Scheme for NoC-Based Systems-on-Chip
DMEMS '10 Proceedings of the 2010 First Workshop on Hardware and Software Implementation and Control of Distributed MEMS
Timing optimization for multisource nets: characterization and optimal repeater insertion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.