Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters

• Authors: A. Nalamalpu;S. Srinivasan;W. P. Burleson
• Venue: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• Year: 2006

Trends in complementary metal-oxide-semiconductor (CMOS) technology and very large scale integration architectures are causing interconnect to play an increasing role in overall performance, power consumption, and design effort. Traditionally, repeaters are used for driving long onchip interconnects. However, recent studies indicate that repeaters are using increasing area, power, and design resources and are inherently limited in how much they can improve the performance (Adler and Friedman, 1998), (Sylvester and Keutzer, 1999), (Cong and Pan, 1999). The unidirectionality of repeaters also limits their applicability in multisourced lines. This paper presents a new circuit called the Booster that compares favorably with repeaters for driving long lines in terms of area, performance, power, and placement sensitivity. Boosters also have the advantage of being bidirectional and providing a low impedance termination to improve signal integrity. Driver edge rates are reduced and peak power is drastically reduced compared to repeaters, thus, improving signal integrity and mitigating inductive effects. Boosters are shown to be more than 20% faster for driving a variety of interconnect loads over conventional repeaters in a 0.16-μm CMOS technology. Boosters are typically inserted three times less frequently than repeaters for optimal performance, resulting in fewer boosters for driving the same interconnect lengths and, hence, saving on area, power, and placement effort. Computer-aided design tools for global interconnect synthesis need to support a wider variety of circuit techniques such as boosters. Other exotic circuit techniques such as differential, dynamic, or low-swing techniques require significantly more custom circuit design, noise analysis, extra timing signals, or extra power supplies and are, hence, cumbersome for automatic interconnect synthesis tools. In contrast, the proposed boosters can be inserted on lines in a straightforward manner much like repeaters. Based on analytical delay models, we derive rules for insertion and sizing of boosters that can easily be incorporated into an interconnect synthesis tool. We formulate design rules that determine: 1) the number of boosters needed; 2) their placements; and 3) device sizes for driving a given interconnect load. The primary objective function is minimizing delay and then area and power. Power analysis is slightly more complex than for repeaters so we present a systematic design approach. A placement sensitivity analysis comparing boosters and repeaters is used to study the effects of realistic placement constraints that arise in microprocessor floorplans. We conclude by discussing various design tradeoffs between repeater and booster-based interconnect designs. We then present other potential applications of boosters in domino logic designs, multisource/multisink buses, and field programmable gate array interconnection network designs in addition to conventional point-to-point interconnection lines