Joint equalization and coding for on-chip bus communication

Authors:
Srinivasa R. Sridhara;Ganesh Balamurugan;Naresh R. Shanbhag
Affiliations:
DSP Solutions R&D Center, Texas Instruments, Dallas, TX and University of Illinois at Urbana-Champaign, Urbana, IL;Circuits Research Laboratory, Intel Corporation, Hillsboro, OR;Coordinated Science Laboratory and the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

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Abstract

In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13- µm CMOS technology show that 1.28 × speedup is achievable by equalization alone and 2.30 × speedup is achievable by joint equalization and coding.