Waveform moment methods for improved interconnection analysis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Delay Models for MCM Interconnects when Response is Non-Monotone
MCMC '97 Proceedings of the 1997 Conference on IEEE Multi-Chip Module Conference
An analytical delay model for RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploiting Crosstalk to Speed up On-Chip Buses
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Joint Equalization and Coding for On-Chip Bus Communication
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A low-power bus design using joint repeater insertion and coding
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Controlling inductive cross-talk and power in off-chip buses using CODECs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A bus architecture for crosstalk elimination in high performance processor design
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Exploiting on-chip data behavior for delay minimization
Proceedings of the 2007 international workshop on System level interconnect prediction
Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Power reduction in on-chip interconnection network by serialization
Proceedings of the 13th international symposium on Low power electronics and design
Bus encoding for simultaneous delay and energy optimization
Proceedings of the 13th international symposium on Low power electronics and design
Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods
Proceedings of the conference on Design, automation and test in Europe
Data handling limits of on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective shielding technique to eliminate crosstalk transitions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An optimization strategy for low energy and high performance for the on-chip interconnect signalling
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Delay-efficient bus encoding techniques
Microprocessors & Microsystems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient CODEC designs for crosstalk avoidance codes based on numeral systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Joint equalization and coding for on-chip bus communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Fibonacci codes for crosstalk avoidance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we study the delay associated with transmission of data through busses. Previous work in this area has presented models for delay assuming a distributed model or a lumped capacitive coupling between wires. In this paper we extend the Elmore delay to account for a distributed model with distributed coupling component and an arbitrary number of lines driven by independent sources. The effect of data patterns is taken into account allowing us to estimate the delay on a sample by sample basis instead of making a worst case assumption. Using this detailed wire delay model, we propose a technique to speed up the communication through a data bus using coding. The idea is to encode the data being transmitted through the bus with the goal of eliminating certain types of transitions that require a large delay. We show that by using proper encoding techniques, the bus can be sped up by a factor of 2.