Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reducing bus delay in submicron technology using coding
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Active shields: a new approach to shielding global wires
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error-correction and crosstalk avoidance in DSM busses
Proceedings of the 2003 international workshop on System-level interconnect prediction
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Optimal shielding/spacing metrics for low power design
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Analysis and Avoidance of Cross-Talk in On-Chip Buses
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
Maximizing throughput over parallel wire structures in the deep submicrometer regime
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Bus Encoding Technique for Power and Cross-talk Minimization
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Delay and Energy Efficient Data Transmission for On-Chip Buses
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Delay and peak power minimization for on-chip buses using temporal redundancy
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Selective shielding: a crosstalk-free bus encoding technique
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
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With CMOS process technology scaling to deep submicron level, propagation delay across long on-chip buses is becoming one of the main performance limiting factors in high-performance designs. Propagation delay is very significant when adjacent wires are transitioning in opposite direction as compared to transitioning in the same direction. As opposite transitions on adjacent wires (called as crosstalk transitions) have significant impact on propagation delay, several bus encoding techniques have been proposed in literature to eliminate such transitions. We propose selective shielding technique to eliminate crosstalk transitions. We show that the selective shielding technique requires ⌈3n/2⌉ wires to encode a n-bit bus. SPICE simulations by considering 90nm technology nodes reveal that, for uniformly distributed random data, our technique achieves nearly 39% (21%) delay savings over 10mm-length uncoded 32-bit bus for pipelined (nonpipelined) data transmission at the cost of nearly 7% energy overhead.