Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
Understanding and addressing the impact of wiring congestion during technology mapping
Proceedings of the 2002 international symposium on Physical design
Narrow bus encoding for low-power DSP systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Proceedings of the 2004 international workshop on System level interconnect prediction
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
SILENT: serialized low energy transmission coding for on-chip interconnection networks
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
MAIA: a framework for networks on chip generation and verification
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reducing the Data Switching Activity on Serial Link Buses
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Integration, the VLSI Journal
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Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Bus encoding for simultaneous delay and energy optimization
Proceedings of the 13th international symposium on Low power electronics and design
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
IEEE Transactions on Computers
Selective shielding technique to eliminate crosstalk transitions
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An integrated logical and physical design flow for deep submicron circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Application-Specific Design Methodology for On-Chip Crossbar Generation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison
International Journal of High Performance Systems Architecture
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Multi-processor systems-on-chip (MPSoC) seek for high performance, scalable and power efficient communication infrastructures. Recent research considers on-chip serial links for communication fabrics as a solution to reduce routing congestion and design complexity. This paper describes a methodology and a tool-chain for design space exploration of temporal encoding schemes, thereafter referred to as NCXplore. NCXplore assists the designer to achieve the best fit as regards both switching activity combined with reduction of crosstalk effects, and performance. A novel class of temporal encoding schemes is also presented to manage switching activity and crosstalk induced delays. NCXplore accepts any encoding technique as a mapping function to investigate crosstalk effects.