Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers
NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects
International Journal of High Performance Systems Architecture
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On-chip serial link buses have been previously proposed as a strong solution to reduce the complexity and/or the energy dissipation of on-chip interconnect fabrics. However, it was noticed that serializing m-bits on a single interconnect (serial-link) increases the overall data switching activity. This paper presents a quantitative analysis of the switching activity of serial links, and provides closed form expressions for the average activity factors. Two transition encoding schemes, to reduce the activity factor of serial links, are discussed and analyzed. The impact of the impact of the encoding schemes on the MCF between neighboring interconnects is also discussed. The analysis shows that both of the schemes provide significant reduction in the average activity factor and energy dissipation reduction, but each in a different range of input activity factors. The two encoding bus schemes were modeled in a 70nm CMOS technology, and compared to an unencoded serial link bus and a parallel line bus. Simulation results show that the transition encoded bus schemes reduce the overall energy dissipation of the unencoded serial link bus by up to 96%.