Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
A spatially-adaptive bus interface for low-switching communication (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Coupling-driven bus design for low-power application-specific systems
Proceedings of the 38th annual Design Automation Conference
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low power address encoding using self-organizing lists
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Analysis and implementation of charge recycling for deep sub-micron buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Narrow bus encoding for low-power DSP systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power-optimal encoding for a DRAM address bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing transitions on memory buses using sector-based encoding technique
Proceedings of the 2002 international symposium on Low power electronics and design
Efficient power reduction techniques for time multiplexed address buses
Proceedings of the 15th international symposium on System Synthesis
Low-power data memory communication for application-specific embedded processors
Proceedings of the 15th international symposium on System Synthesis
Bus optimization for low-power data path synthesis based on network flow method
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An integrated data path optimization for low power based on network flow method
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A bus energy model for deep submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Low Power Encoding Techniques for Dynamically Reconfigurable Hardware
The Journal of Supercomputing
Weight-Based Bus-Invert Coding for Low-Power Applications
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
A Low Power-Delay Product Page-Based Address Bus Coding Method
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Memory Bus Encoding for Low Power: A Tutorial
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Energy-reliability trade-off for NoCs
Networks on chip
High-level synthesis for low power based on network flow method
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Adaptive low-power address encoding techniques using self-organizing lists
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
A dictionary-based en/decoding scheme for low-power data buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Frequent value encoding for low power data buses
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power Efficiency through Application-Specific Instruction Memory Transformations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Energy optimization in memory address bus structure for application-specific systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Abridged addressing: a low power memory addressing strategy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
BEAM: bus encoding based on instruction-set-aware memories
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Irredundant address bus encoding techniques based on adaptive codebooks for low power
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reducing the Data Switching Activity on Serial Link Buses
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Proceedings of the conference on Design, automation and test in Europe
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Energy-efficient encoding techniques for off-chip data buses
ACM Transactions on Embedded Computing Systems (TECS)
Power consumption of fault tolerant busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
On the distribution of runs of ones in binary strings
Computers & Mathematics with Applications
Serial-link bus: a low-power on-chip bus architecture
IEEE Transactions on Circuits and Systems Part I: Regular Papers
An efficient segmental bus-invert coding method for instruction memory data bus switching reduction
EURASIP Journal on Embedded Systems
Journal of Systems Architecture: the EUROMICRO Journal
Interframe bus encoding technique and architecture for MPEG-4 AVC/H.264 video compression
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
GPH: A group-based partitioning scheme for reducing total power consumption of parallel buses
Microprocessors & Microsystems
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Practical and theoretical considerations on low-power probability-codes for networks-on-chip
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Approximate arithmetic coding for bus transition reduction in low power designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequence-switch coding for low-power data transmission
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dynamic memory access management for high-performance DSP applications using high-level synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Context-independent codes for off-chip interconnects
PACS'04 Proceedings of the 4th international conference on Power-Aware Computer Systems
Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Automatic design of low-power encoders using reversible circuit synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high-capacitance buses where the extra power dissipation due to the encoder and decoder circuitry is offset by the power savings at the bus. In this framework, a data source (characterized in a probabilistic manner) is first passed through a decorrelating function f/sub 1/. Next, a variant of entropy coding function f/sub 2/ is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f/sub 1/ and f/sub 2/ are proposed. Simulation results with an encoding scheme for data buses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/b in 1.2 /spl mu/m CMOS technology. For a typical value for bus capacitance of 50 pF/b, there is a 36% reduction in power dissipation and eight times more power savings compared to existing schemes. Simulation results with an encoding scheme for instruction address buses indicate an average reduction in transition activity by a factor of 1.5 times over known coding schemes.