Two dimensional codes for low power
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
System-level power optimization of special purpose applications: the beach solution
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Exploiting the locality of memory references to reduce the address bus energy
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Using complementation and resequencing to minimize transitions
DAC '98 Proceedings of the 35th annual Design Automation Conference
Partial bus-invert coding for power optimization of system level bus
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
A performance comparison of contemporary DRAM architectures
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
On reducing transitions through data modifications
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Synthesis of low-overhead interfaces for power-efficient communication over wide buses
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A coding framework for low-power address and data busses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Bus encoding for low-power high-performance memory systems
Proceedings of the 37th Annual Design Automation Conference
Power-optimal encoding for DRAM address bus (poster session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Address bus encoding techniques for system-level power optimization
Proceedings of the conference on Design, automation and test in Europe
Low power techniques for address encoding and memory allocation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Saving Power in the Control Path of Embedded Processors
IEEE Design & Test
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Coding a terminated bus for low power
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
Performance analysis of different arbitration algorithms of the AMBA AHB bus
Proceedings of the 41st annual Design Automation Conference
Energy-Efficient Color Approximation for Digital LCD Interfaces
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Optimal memoryless encoding for low power off-chip data buses
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
| Hi-index | 0.00 |
This paper contains a tutorial on bus-encoding techniques that target low power dissipation. Three general classes of codes, i.e., algebraic, permutation-based, and probability-based, are reviewed. A new mathematical framework for unifying the power-aware algebraic coding techniques based on the notion of leader sets is also presented.