Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Memory Bus Encoding for Low Power: A Tutorial
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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Interconnect area and energy dissipation are critical factors in any system designed today. In this work, we present techniques to help reduce area/cost and energy dissipation of address buses with significant temporal redundancy. We describe two encoding techniques for such buses, called pattern adjuster (PA) encoding and dynamic charge/discharge encoding (DCDE), that use simple hardware and no extra bus lines for control signals. Results show that, using PA encoding, self energy reduces by 18-38%, coupling toggle energy by 19-96%, and coupling charge/discharge energy by 14-40%. In addition, with DCDE applied on top of PA, coupling charge/discharge energy reduces by up to 48%. Overall, up to 25% address bus energy savings can be obtained using our techniques compared to the energy dissipation of the original bus, with 26-79% reduction in the number of bus lines. Our techniques use very simple hardware and will have negligible encoding/decoding latencies that are much lower than those of low-power bus encoding schemes.