GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
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Minimizing the area/cost and power consumption of communicationcomponents (address, instruction, and data buses and associatedhardware like I/O pins, pads, and buffers) is becoming important inmodern microprocessors. Currently, utilization of buses is nottaken into account during design of many bus systems. This may leadto underutilization of many buses during actual operation. In thispaper, we propose a scheme that exploits the underutilization ofaddress buses to result in a cost-effective and energy-efficientbus system design. This is accomplished by using buses of narrowwidth, new encoding schemes for narrow buses, and with design ofhardware that result in only a minimal impact on performance andpower consumption. We show the efficacy of our schemes usingsimulations on a validated Alpha 21264 model for Simple Scalarandusing physical address traces from 14 SPEC CPU2000 benchmarks.