Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Working-zone encoding for reducing the energy in microprocessor address buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Information-theoretic bounds on average signal transition activity
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-energy for deep-submicron address buses
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Coupling-driven signal encoding scheme for low-power interface design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses
Proceedings of the 2004 international symposium on Low power electronics and design
Low-power instruction bus encoding for embedded processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal partitioned fault-tolerant bus layout for reducing power in nanometer designs
Proceedings of the 2006 international symposium on Physical design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
An energy-efficient temporal encoding circuit technique for on-chip high performance buses
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
An analysis of timing violations due to spatially distributed thermal effects in global wires
Proceedings of the 44th annual Design Automation Conference
Bus encoding schemes for minimizing delay in VLSI interconnects
Proceedings of the 20th annual conference on Integrated circuits and systems design
Dynamic tag reduction for low-power caches in embedded systems with virtual memory
International Journal of Parallel Programming
DS2IS: Dictionary-based segmented inversion scheme for low power dynamic bus design
Journal of Systems Architecture: the EUROMICRO Journal
Bandwidth-centric optimisation for area-constrained links with crosstalk avoidance methods
Proceedings of the conference on Design, automation and test in Europe
Sign Bit Reduction Encoding For Low Power Applications
Journal of Signal Processing Systems
On the distribution of runs of ones in binary strings
Computers & Mathematics with Applications
Proceedings of the 20th symposium on Great lakes symposium on VLSI
A data capturing method for buses on chip
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Efficient RC low-power bus encoding methods for crosstalk reduction
Integration, the VLSI Journal
Reliable network-on-chip design for multi-core system-on-chip
The Journal of Supercomputing
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus-switch coding for reducing power dissipation in off-chip buses
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Partial bus-invert bus encoding schemes for low-power DSP systems considering inter-wire capacitance
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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The coupling capacitances between on-chip bus lines become dominant in deep-submicron technologies. Coding to reduce the switching activity of the individual lines was enough to reduce power on buses in older technologies, but new coding techniques that reduce the coupling activity between lines are needed for deep-submicron buses. One such coding technique uses the simple observation that coupling capacitances are always charged and discharged by activity on neighboring bus lines, where one line has an odd number and the other has an even number (if bus lines are numbered "in-order"). We thus propose to reduce the coupling activity by independently controlling the odd and even bus lines with two separate lines, the Odd Invert, and Even Invert line, respectively. We obtain significant reductions in power simply by comparing the coupling activity for the four possible cases of the Odd and Even Invert lines (00, 01, 10, 11), and then choosing the value with the smallest coupling activity to transmit on the bus. Even after encoding, the coupling activity for a pair of bus lines is still strongly dependent on the data. In particular the toggling sequences 01→10 and 10→01 result in 4 times more coupling energy dissipation than other coupling events. We thus propose a targeted Two-Phase transfer in order to reduce total power only on the pairs of lines that carry such toggling events.