A spacing algorithm for performance enhancement and cross-talk reduction
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Power optimization of system-level address buses based on software profiling
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs
Proceedings of the 38th annual Design Automation Conference
Partial bus-invert coding for power optimization of application-specific systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Odd/even bus invert with two-phase transfer for buses with coupling
Proceedings of the 2002 international symposium on Low power electronics and design
Coding Theory: The Essentials
Essentials of Computer Organization and Architecture
Essentials of Computer Organization and Architecture
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Coding Scheme for Low Energy Consumption Fault-Tolerant Bus
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Coupling Noise Analysis for VLIS and ULSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect sizing and spacing with consideration of coupling capacitance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Coupling-aware high-level interconnect synthesis [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DS2IS: Dictionary-based segmented inversion scheme for low power dynamic bus design
Journal of Systems Architecture: the EUROMICRO Journal
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As technology scales down to nanometer dimensions, coupling capacitances between adjacent bus wires grow rapidly, and have a significant impact on power consumption and signal integrity of an integrated circuit. As buses are major components of a design, it is important to design fault-tolerant buses that dissipate less power and raise reliability without sacrificing performance. In this paper, we address the problem of using Hamming single error correcting code by optimizing both wire permutation and spacing. We propose an efficient polynomial time algorithm which applies graph theory for this optimization problem. Unlike previous studies [17], our approach can be applied to high bandwidth fault-tolerant buses to efficiently reduce the coupling capacitances by utilizing available space. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs for evaluating energy reduction. The results show that our approach can save energy up to 43% for the best case, and 30% for the worst with 20 x dmin ( min is the mininal permitted wire distance) additional width on RLC model. Besides, we also provided comprehensive comparisons in experimental result section for different fault-tolerant bus layout methods and error correction codes.